linux-kernel - Re: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base

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Message-ID: <20150811235451.GA26614@codeaurora.org>
Date:	Tue, 11 Aug 2015 16:54:52 -0700
From:	Stephen Boyd <sboyd@...eaurora.org>
To:	dinguyen@...nsource.altera.com
Cc:	mturquette@...libre.com, dinh.linux@...il.com,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCHv2] clk: socfpga: Add a second parent option for the
 dbg_base_clk

On 07/24, dinguyen@...nsource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@...nsource.altera.com>
> 
> The debug base clock can be bypassed from the main PLL to the OSC1 clock.
> The bypass register is the staysoc1(0x10) register that is in the clock
> manager.
> 
> This patch adds the option to get the correct parent for the debug base
> clock.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@...nsource.altera.com>
> ---

Applied to clk-next

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