linux-kernel - Re: RFC: prepare for struct scatterlist entries without page backing

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Message-ID: <CAP6odjhfTHzgEivDUxXyU=VBG4U85ETxv1gcogE9GVGoGQ37-w@mail.gmail.com>
Date:	Wed, 12 Aug 2015 10:56:26 -0700
From:	Grant Grundler <grantgrundler@...il.com>
To:	James Bottomley <James.Bottomley@...senpartnership.com>
Cc:	Christoph Hellwig <hch@....de>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	axboe@...nel.dk, dan.j.williams@...el.com, vgupta@...opsys.com,
	hskinnemoen@...il.com, egtvedt@...fundet.no, realmz6@...il.com,
	dhowells@...hat.com, monstr@...str.eu, x86@...nel.org,
	David Woodhouse <dwmw2@...radead.org>,
	alex.williamson@...hat.com,
	Grant Grundler <grundler@...isc-linux.org>,
	open list <linux-kernel@...r.kernel.org>,
	linux-arch@...r.kernel.org, linux-alpha@...r.kernel.org,
	linux-ia64@...r.kernel.org, linux-metag@...r.kernel.org,
	linux-mips@...ux-mips.org,
	linux-parisc <linux-parisc@...r.kernel.org>,
	linuxppc-dev@...ts.ozlabs.org, linux-s390@...r.kernel.org,
	sparclinux@...r.kernel.org, linux-xtensa@...ux-xtensa.org,
	linux-nvdimm@...1.01.org, linux-media@...r.kernel.org
Subject: Re: RFC: prepare for struct scatterlist entries without page backing

On Wed, Aug 12, 2015 at 10:00 AM, James Bottomley
<James.Bottomley@...senpartnership.com> wrote:
> On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote:
...
>> However the ccio (parisc) and sba_iommu (parisc & ia64) IOMMUs seem
>> to be operate mostly on virtual addresses.  It's a fairly odd concept
>> that I don't fully grasp, so I'll need some help with those if we want
>> to bring this forward.

James explained the primary function of IOMMUs on parisc (DMA-Cache
coherency) much better than I ever could.

Three more observations:
1) the IOMMU can be bypassed by 64-bit DMA devices on IA64.

2) IOMMU enables 32-bit DMA devices to reach > 32-bit physical memory
and thus avoiding bounce buffers. parisc and older IA-64 have some
32-bit PCI devices - e.g. IDE boot HDD.

3) IOMMU acts as a proxy for IO devices by fetching cachelines of data
for PA-RISC systems whose memory controllers ONLY serve cacheline
sized transactions. ie. 32-bit DMA results in the IOMMU fetching the
cacheline and updating just the 32-bits in a DMA cache coherent
fashion.

Bonus thought:
4) IOMMU can improve DMA performance in some cases using "hints"
provided by the OS (e.g. prefetching DMA data or using READ_CURRENT
bus transactions instead of normal memory fetches.)

cheers,
grant
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