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Message-ID: <20150813071626.GA21239@gondor.apana.org.au>
Date: Thu, 13 Aug 2015 15:16:26 +0800
From: Herbert Xu <herbert@...dor.apana.org.au>
To: Chen-Yu Tsai <wens@...e.org>
Cc: Corentin Labbe <clabbe.montjoie@...il.com>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
linux-crypto@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/3] ARM: sun6i: Support Security System crypto engine
On Tue, Aug 11, 2015 at 01:32:54PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series enables support for the crypto engine found in sun6i, or
> Allwinner A31/A31s SoCs. The crypto engine is the same hardware as on
> earlier sun4i/sun7i (A10/A20), with the only difference being the reset
> control is separated out of the clock gate control.
>
> The same hardware is also available on the A33, but not the A23. Support
> for this requires additions to the clock driver, and will be submitted
> separately once things are clear on how to proceed. I already have a
> proof of concept working.
>
>
> Patch 1 adds an optional reset control property to the sunxi-ss binding.
>
> Patch 2 adds optional reset control support to the sunxi-ss driver.
>
> Patch 3 enables the crypto engine on sun6i, by adding the module clock and
> device node.
All applied. Thanks.
--
Email: Herbert Xu <herbert@...dor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
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