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Message-Id: <1439465645-22584-9-git-send-email-suzuki.poulose@arm.com>
Date: Thu, 13 Aug 2015 12:33:58 +0100
From: "Suzuki K. Poulose" <suzuki.poulose@....com>
To: linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
kvmarm@...ts.cs.columbia.edu, catalin.marinas@....com,
will.deacon@....com, mark.rutland@....com, marc.zyngier@....com,
"Suzuki K. Poulose" <suzuki.poulose@....com>,
Christoffer Dall <christoffer.dall@...aro.org>
Subject: [PATCH 08/14] arm64: kvm: Fix {V}TCR_EL2_TG0 mask
From: "Suzuki K. Poulose" <suzuki.poulose@....com>
{V}TCR_EL2_TG0 is a 2bit wide field, where:
00 - 4K
01 - 64K
10 - 16K
But we use only 1 bit, which has worked well so far since
we never cared about 16K. Fix it for 16K support.
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Will Deacon <will.deacon@....com>
Cc: Marc Zyngier <marc.zyngier@....com>
Cc: Christoffer Dall <christoffer.dall@...aro.org>
Cc: kvmarm@...ts.cs.columbia.edu
Acked-by: Mark Rutland <mark.rutland@....com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@....com>
---
arch/arm64/include/asm/kvm_arm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index ac6fafb..52dc9cc 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -98,7 +98,7 @@
#define TCR_EL2_TBI (1 << 20)
#define TCR_EL2_PS (7 << 16)
#define TCR_EL2_PS_40B (2 << 16)
-#define TCR_EL2_TG0 (1 << 14)
+#define TCR_EL2_TG0 (3 << 14)
#define TCR_EL2_SH0 (3 << 12)
#define TCR_EL2_ORGN0 (3 << 10)
#define TCR_EL2_IRGN0 (3 << 8)
@@ -110,7 +110,7 @@
/* VTCR_EL2 Registers bits */
#define VTCR_EL2_PS_MASK (7 << 16)
-#define VTCR_EL2_TG0_MASK (1 << 14)
+#define VTCR_EL2_TG0_MASK (3 << 14)
#define VTCR_EL2_TG0_4K (0 << 14)
#define VTCR_EL2_TG0_64K (1 << 14)
#define VTCR_EL2_SH0_MASK (3 << 12)
--
1.7.9.5
--
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