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Message-ID: <1439564462-21252-1-git-send-email-suneel.garapati@xilinx.com>
Date: Fri, 14 Aug 2015 20:31:01 +0530
From: Suneel Garapati <suneel.garapati@...inx.com>
To: <rtc-linux@...glegroups.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: Alexandre Belloni <alexandre.belloni@...e-electrons.com>,
<michals@...inx.com>, <sorenb@...inx.com>,
Alessandro Zummo <a.zummo@...ertech.it>,
Suneel Garapati <suneel.garapati@...inx.com>
Subject: [PATCH v3 1/3] devicetree: bindings: rtc: add bindings for xilinx zynqmp rtc
adds file for description on device node bindings for RTC
found on Xilinx Zynq Ultrascale+ MPSoC.
Signed-off-by: Suneel Garapati <suneel.garapati@...inx.com>
---
Changes v3
- none
Changes v2
- add examples for interrupt-names
- change alm to alarm
---
Documentation/devicetree/bindings/rtc/xlnx-rtc.txt | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
diff --git a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
new file mode 100644
index 0000000..0df6f01
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
@@ -0,0 +1,25 @@
+* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
+
+RTC controller for the Xilinx Zynq MPSoC Real Time Clock
+Separate IRQ lines for seconds and alarm
+
+Required properties:
+- compatible: Should be "xlnx,zynqmp-rtc"
+- reg: Physical base address of the controller and length
+ of memory mapped region.
+- interrupts: IRQ lines for the RTC.
+- interrupt-names: interrupt line names eg. "sec" "alarm"
+
+Optional:
+- calibration: calibration value for 1 sec period which will
+ be programmed directly to calibration register
+
+Example:
+rtc: rtc@...60000 {
+ compatible = "xlnx,zynqmp-rtc";
+ reg = <0x0 0xffa60000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 26 4>, <0 27 4>;
+ interrupt-names = "alarm", "sec";
+ calibration = <0x198233>;
+};
--
2.1.2
--
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