linux-kernel - Re: [PATCH v10 3/8] add fpga manager core

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Message-ID: <alpine.DEB.2.02.1508141026280.661@linuxheads99>
Date:	Fri, 14 Aug 2015 10:46:58 -0500
From:	atull <atull@...nsource.altera.com>
To:	Moritz Fischer <moritz.fischer@...us.com>
CC:	Greg KH <gregkh@...uxfoundation.org>,
	Jason Gunthorpe <jgunthorpe@...idianresearch.com>,
	<hpa@...or.com>, Michal Simek <monstr@...str.eu>,
	Michal Simek <michal.simek@...inx.com>,
	<rdunlap@...radead.org>, <linux-kernel@...r.kernel.org>,
	<devicetree@...r.kernel.org>,
	Pantelis Antoniou <pantelis.antoniou@...sulko.com>,
	<robh+dt@...nel.org>, Grant Likely <grant.likely@...aro.org>,
	<iws@...o.caltech.edu>, <linux-doc@...r.kernel.org>,
	<pavel@...x.de>, <broonie@...nel.org>,
	"Philip Balister" <philip@...ister.org>, <rubini@...dd.com>,
	<s.trumtrar@...gutronix.de>, <jason@...edaemon.net>,
	<kyle.teske@...com>, Nicolas Pitre <nico@...aro.org>,
	<balbi@...com>, <m.chehab@...sung.com>,
	David Brown <davidb@...eaurora.org>,
	Rob Landley <rob@...dley.net>, <davem@...emloft.net>,
	<cesarb@...arb.net>, <sameo@...ux.intel.com>,
	<akpm@...ux-foundation.org>,
	Linus Walleij <linus.walleij@...aro.org>, <pawel.moll@....com>,
	<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	<devel@...verdev.osuosl.org>, Petr Cvek <petr.cvek@....cz>,
	Alan Tull <delicious.quinoa@...il.com>, <yvanderv@...era.com>,
	<dinguyen@...nsource.altera.com>
Subject: Re: [PATCH v10 3/8] add fpga manager core

On Fri, 14 Aug 2015, atull wrote:

> On Fri, 14 Aug 2015, Moritz Fischer wrote:
> 
> > Hi Alan,
> > 
> > I've updated my Zynq driver (it can be found in an older version
> > against your v8 in the Xilinx tree, too)
> > 
> > https://github.com/mfischer/linux/tree/alan-fpga-mgr-v10
> 
> Since we are both already using this and have been for a while now, I hope it
> can go up into the mainstream instead of continuing to exist only in Altera
> and Xilinx's git trees.
> 

Hi Moritz,

I fetched your git tree and took a look at your low level driver.

I had a some feedback.  write_complete() is a blocking call, waiting for the
FPGA to go into operating state and timing out (ETIMEDOUT) if necessary.  The
fpga-mgr.c framework is assuming that when write_complete exits with status 0,
that means that the FPGA is in operating state.  That's why it's proper for us
to add "mgr->state = FPGA_MGR_STATE_OPERATING" after write_complete returns
success as you noted.  My suggestion is that your write_complete() should check
status in this way.  Whatever error codes it returns will get propagated.

Also, I'm wondering how the simple-fpga-bus stuff looks to you now that you've
had it for a little while.

Thank,
Alan
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