linux-kernel - Re: Re: [PATCH] arm: Adding support for atomic half word exchange

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Message-id: <1707387422.329291440052843653.JavaMail.weblogic@ep2mlwas04c>
Date:	Thu, 20 Aug 2015 06:40:46 +0000 (GMT)
From:	Sarbojit Ganguly <ganguly.s@...sung.com>
To:	Catalin Marinas <catalin.marinas@....com>,
	Sarbojit Ganguly <ganguly.s@...sung.com>, will.deacon@....com,
	linux-arm-kernel@...ts.infradead.org
Cc:	SHARAN ALLUR <sharan.allur@...sung.com>,
	VIKRAM MUPPARTHI <vikram.m@...sung.com>,
	"peterz@...radead.org" <peterz@...radead.org>,
	"Waiman.Long@...com" <Waiman.Long@...com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"torvalds@...ux-foundation.org" <torvalds@...ux-foundation.org>
Subject: Re: Re: [PATCH] arm: Adding support for atomic half word exchange

My apologies, the e-mail editor was not configured properly.
CC'ed to relevant maintainers and reposting once again with proper formatting.

Since 16 bit half word exchange was not there and MCS based qspinlock
by Waiman's xchg_tail() requires an atomic exchange on a half word, 
here is a small modification to __xchg() code to support the exchange.
ARMv6 and lower does not have support for LDREXH, so we need to make sure things
do not break when we're compiling on ARMv6.

Signed-off-by: Sarbojit Ganguly <ganguly.s@...sung.com>
---
 arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 1692a05..547101d 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
                        : "r" (x), "r" (ptr)
                        : "memory", "cc");
                break;
+#if !defined (CONFIG_CPU_V6)
+               /*
+                * Halfword exclusive exchange
+                * This is new implementation as qspinlock
+                * wants 16 bit atomic CAS.
+                * This is not supported on ARMv6.
+                */
+       case 2:
+               asm volatile("@ __xchg2\n"
+               "1:     ldrexh  %0, [%3]\n"
+               "       strexh  %1, %2, [%3]\n"
+               "       teq     %1, #0\n"
+               "       bne     1b"
+               : "=&r" (ret), "=&r" (tmp)
+               : "r" (x), "r" (ptr)
+               : "memory", "cc");
+               break;
+#endif
        case 4:
                asm volatile("@ __xchg4\n"
                "1:     ldrex   %0, [%3]\n"



Regards,
Sarbojit

------- Original Message -------
Sender : Catalin Marinas<catalin.marinas@....com>
Date : Aug 19, 2015 21:43 (GMT+05:30)
Title : Re: [PATCH] arm: Adding support for atomic half word exchange

On Tue, Aug 18, 2015 at 09:17:53AM +0100, Sarbojit Ganguly wrote:
> 
> 
> Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange.
> ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6.

First of all, please wrap the text appropriately.

Secondly, you need to cc the relevant maintainer and mailing list (try
running ./scripts/get_maintainer.pl on this patch to get some hints).

-- 
Catalin