linux-kernel - [tip:irq/core] irqchip: Add documentation for the bcm2836 interrupt controller

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Message-ID: <tip-815e7a31c3f7929f371da9c7e9ee91cfd52ef453@git.kernel.org>
Date:	Thu, 20 Aug 2015 13:43:14 -0700
From:	tip-bot for Eric Anholt <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	mingo@...nel.org, swarren@...dotorg.org, hpa@...or.com,
	eric@...olt.net, jason@...edaemon.net,
	linux-kernel@...r.kernel.org, lee@...nel.org, tglx@...utronix.de
Subject: [tip:irq/core] irqchip:
  Add documentation for the bcm2836 interrupt controller

Commit-ID:  815e7a31c3f7929f371da9c7e9ee91cfd52ef453
Gitweb:     http://git.kernel.org/tip/815e7a31c3f7929f371da9c7e9ee91cfd52ef453
Author:     Eric Anholt <eric@...olt.net>
AuthorDate: Thu, 6 Aug 2015 16:00:32 -0700
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Thu, 20 Aug 2015 22:38:42 +0200

irqchip: Add documentation for the bcm2836 interrupt controller

This is a new per-cpu root interrupt controller on the Raspberry Pi 2,
which will chain to the bcm2835 interrupt controller for peripheral
interrupts.

Signed-off-by: Eric Anholt <eric@...olt.net>
Acked-by: Stephen Warren <swarren@...dotorg.org>
Cc: linux-rpi-kernel@...ts.infradead.org
Cc: Lee Jones <lee@...nel.org>
Cc: Jason Cooper <jason@...edaemon.net>
Cc: linux-arm-kernel@...ts.infradead.org
Link: http://lkml.kernel.org/r/1438902033-31477-4-git-send-email-eric@anholt.net
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 .../interrupt-controller/brcm,bcm2836-l1-intc.txt  | 37 ++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt
new file mode 100644
index 0000000..f320dcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt
@@ -0,0 +1,37 @@
+BCM2836 per-CPU interrupt controller
+
+The BCM2836 has a per-cpu interrupt controller for the timer, PMU
+events, and SMP IPIs.  One of the CPUs may receive interrupts for the
+peripheral (GPU) events, which chain to the BCM2835-style interrupt
+controller.
+
+Required properties:
+
+- compatible:	 	Should be "brcm,bcm2836-l1-intc"
+- reg:			Specifies base physical address and size of the
+			  registers
+- interrupt-controller:	Identifies the node as an interrupt controller
+- #interrupt-cells:	Specifies the number of cells needed to encode an
+			  interrupt source. The value shall be 1
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+The interrupt sources are as follows:
+
+0: CNTPSIRQ
+1: CNTPNSIRQ
+2: CNTHPIRQ
+3: CNTVIRQ
+8: GPU_FAST
+9: PMU_FAST
+
+Example:
+
+local_intc: local_intc {
+	compatible = "brcm,bcm2836-l1-intc";
+	reg = <0x40000000 0x100>;
+	interrupt-controller;
+	#interrupt-cells = <1>;
+	interrupt-parent = <&local_intc>;
+};
--
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