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Message-ID: <55D6D4F6.4020100@xilinx.com>
Date: Fri, 21 Aug 2015 09:36:22 +0200
From: Michal Simek <michal.simek@...inx.com>
To: Moritz Fischer <moritz.fischer@...us.com>,
Appana Durga Kedareswara Rao <appana.durga.rao@...inx.com>
CC: Appana Durga Kedareswara Rao <appanad@...inx.com>,
"vinod.koul@...el.com" <vinod.koul@...el.com>,
"dan.j.williams@...el.com" <dan.j.williams@...el.com>,
Soren Brinkmann <sorenb@...inx.com>,
"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
Anirudha Sarangi <anirudh@...inx.com>
Subject: Re: [RESEND PATCH] dmaengine: Add Xilinx AXI Direct Memory Access
Engine driver support
Hi,
On 08/21/2015 03:16 AM, Moritz Fischer wrote:
> Hi,
>
> your MUA produces funny messages somehow ...
> The driver did not probe for me in it's current form as the bindings
> were missing interrupt parents for the interrupts...
It is just a question where interrupt parent is listed. I have seen that
some SoCs are just setting up at one location for all IPs.
I remember some discussions that some properties don't need to be
documented again and again. That's why the question is if they are
really needed to be documented in the binding doc because it is just
documentation duplication in every binding document.
Definitely if you miss it in the binding doc, feel free to send the
patch and update it.
Thanks,
Michal
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