Date:	Sat, 22 Aug 2015 16:17:36 +0530
From:	punnaiah choudary kalluri <punnaia@...inx.com>
To:	Moritz Fischer <moritz.fischer@...us.com>
Cc:	Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@...inx.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"pawel.moll@....com" <pawel.moll@....com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Michal Simek <michal.simek@...inx.com>,
	Vinod Koul <vinod.koul@...el.com>, dan.j.williams@...el.com,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Punnaiah Choudary <kpc528@...il.com>,
	dmaengine@...r.kernel.org,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device
 tree binding documentation

Hi Moritz,

  Thanks. I will take care of these suggestions in next version

Regards,
Punnaiah

On Fri, Aug 21, 2015 at 10:12 PM, Moritz Fischer
<moritz.fischer@...us.com> wrote:
> Hi all,
>
> sorry for HTML mail spam last night ... couple of nits below
>
> On Wed, Aug 5, 2015 at 8:19 PM, Punnaiah Choudary Kalluri
> <punnaiah.choudary.kalluri@...inx.com> wrote:
>> Device-tree binding documentation for Xilinx zynqmp dma engine used in
>> Zynq UltraScale+ MPSoC.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@...inx.com>
>> ---
>> Changes in v4:
>> - None
>> Changes in v3:
>> - None
>> Changes in v2:
>> - None
>> ---
>>  .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  |   61 ++++++++++++++++++++
>>  1 files changed, 61 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>>
>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> new file mode 100644
>> index 0000000..e4f92b9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> @@ -0,0 +1,61 @@
>> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
>> +memory to device and device to memory transfers. It also has flow
>> +control and rate control support for slave/peripheral dma access.
>
> How about: The Xilinx ZynqMP DMA engine does support memory to memory transfers,
> memory to device and device to memory transfers. It also has flow
> control and rate control
> support for slave / peripheral DMA access.
>> +
>> +Required properties:
>> +- compatible: Should be "xlnx,zynqmp-dma-1.0"
>> +- #dma-cells: Should be <1>, a single cell holding a line request number
>> +- reg: Memory map for module access
>> +- interrupt-parent: Interrupt controller the interrupt is routed through
>> +- interrupts: Should contain DMA channel interrupt
>> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64
>> +
>> +Optional properties:
>> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter
>> +                  gather dma mode
> s/dma/DMA
>> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
>> +                source AXI transaction
>> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
> (Maybe) s/Tells/Determines/
>> +- xlnx,src-issue: Number of AXI outstanding transactions on source side
>> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
>> +                       descriptor read are marked Non-coherent
> (Maybe) s/Tells/Determines/
>> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
>> +                       source descriptor payload are marked Non-coherent
> same
>> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
>> +                       dst descriptor payload are marked Non-coherent
>> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
>> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read
>> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch.
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read
>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write
>> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values
>> +                     i.e 1,2,4,8 and 16
>> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values
>> +                     i.e 1,2,4,8 and 16
>> +
>> +Example:
>> +++++++++
>> +fpd_dma_chan1: dma@...00000 {
>> +       compatible = "xlnx,zynqmp-dma-1.0";
>> +       reg = <0x0 0xFD500000 0x1000>;
>> +       #dma_cells = <1>;
> #dma-cells = <1>;
>> +       interrupt-parent = <&gic>;
>> +       interrupts = <0 117 4>;
>> +       xlnx,bus-width = <128>;
>> +       xlnx,include-sg;
>> +       xlnx,overfetch;
>> +       xlnx,ratectrl = <0>;
>> +       xlnx,src-issue = <16>;
>> +       xlnx,desc-axi-cohrnt;
>> +       xlnx,src-axi-cohrnt;
>> +       xlnx,dst-axi-cohrnt;
>> +       xlnx,desc-axi-qos = <0>;
>> +       xlnx,desc-axi-cache = <0>;
>> +       xlnx,src-axi-qos = <0>;
>> +       xlnx,src-axi-cache = <2>;
>> +       xlnx,dst-axi-qos = <0>;
>> +       xlnx,dst-axi-cache = <2>;
>> +       xlnx,src-burst-len = <4>;
>> +       xlnx,dst-burst-len = <4>;
>> +};
>> --
>> 1.7.4
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@...ts.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> Cheers,
>
> Moritz
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