linux-kernel - Re: [PATCH 1/3] ARM: uniphier: add outer cache support

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Date:	Mon, 24 Aug 2015 21:59:51 +0200
From:	Arnd Bergmann <arnd@...db.de>
To:	Masahiro Yamada <yamada.masahiro@...ionext.com>
Cc:	arm@...nel.org, Jiri Slaby <jslaby@...e.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	Kumar Gala <galak@...eaurora.org>,
	Jungseung Lee <js07.lee@...il.com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Rob Herring <robh+dt@...nel.org>, Tejun Heo <tj@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	devicetree@...r.kernel.org,
	Mauro Carvalho Chehab <mchehab@....samsung.com>,
	Russell King <linux@....linux.org.uk>,
	linux-arm-kernel@...ts.infradead.org,
	Nathan Lynch <nathan_lynch@...tor.com>,
	Kees Cook <keescook@...omium.org>,
	Paul Bolle <pebolle@...cali.nl>,
	Greg KH <gregkh@...uxfoundation.org>,
	linux-kernel@...r.kernel.org,
	"David S. Miller" <davem@...emloft.net>,
	Joe Perches <joe@...ches.com>,
	Uwe Kleine-König 
	<u.kleine-koenig@...gutronix.de>,
	Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH 1/3] ARM: uniphier: add outer cache support

On Monday 24 August 2015 11:18:10 Masahiro Yamada wrote:
> diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
> new file mode 100644
> index 0000000..6428289
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
> @@ -0,0 +1,30 @@
> +UniPhier outer cache controller
> +
> +UniPhier SoCs are integrated with a level 2 cache controller that resides
> +outside of the ARM cores, some of them also have a level 3 cache controller.
> +
> +Required properties:
> +- compatible: should be one of the followings:
> +       "socionext,uniphier-l2-cache"   (L2 cache)
> +       "socionext,uniphier-l3-cache"   (L3 cache)
> +- reg: offsets and lengths of the register sets for the device.  It should
> +  contain 3 regions: control registers, revision registers, operation
> +  registers, in this order.
> +
> +The L2 cache must exist to use the L3 cache; adding only an L3 cache device
> +node to the device tree causes the initialization failure of the whole outer
> +cache system.
> 

How much does this outer cache have in common with the l2x0/pl310 cache
controller model? Would it make sense to at least share the
common entry point at l2x0_of_init() so you don't need to call it from
the platform file?

	Arnd
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