linux-kernel - [PATCH] pinctrl: sh-pfc: Add R8A7795 PFC support

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Message-ID: <87fv377tg1.wl%kuninori.morimoto.gx@renesas.com>
Date:	Tue, 25 Aug 2015 06:54:10 +0000
From:	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>
To:	Simon <horms@...ge.net.au>,
	Laurent Pinchart <laurent.pinchart@...asonboard.com>,
	Linus Walleij <linus.walleij@...aro.org>
CC:	Magnus <magnus.damm@...il.com>, <linux-sh@...r.kernel.org>,
	<linux-gpio@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH] pinctrl: sh-pfc: Add R8A7795 PFC support

From: Takeshi Kihara <takeshi.kihara.df@...esas.com>

Add PFC support for the R8A7795 SoC including pin groups.
It is including EthernetAVB, DU, HDMI, MSOIF, SDHI, USB2.0, USB3.0

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...esas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>
---
> Laurent, LinusW

I guess upstream ML can't accept it, because this is very large size patch.
and unfortunately it is difficult to split it.
But, please review it.

Renesas r8a7795 initial SoC/board support patch-set depends on this patch.
Renesas SoC series maintainer is Simon and Magnus.
Simon can accept (?) this patch as part of Renesas new SoC if LinusW/Laurent
can give it Ack. Or Simon can merge/base your branch.
I'm not sure which one is good choice

 drivers/pinctrl/sh-pfc/Kconfig       |    5 +
 drivers/pinctrl/sh-pfc/Makefile      |    1 +
 drivers/pinctrl/sh-pfc/core.c        |    6 +
 drivers/pinctrl/sh-pfc/core.h        |    1 +
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 4299 ++++++++++++++++++++++++++++++++++
 5 files changed, 4312 insertions(+)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7795.c

diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 8e024c9..5068b47 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -65,6 +65,11 @@ config PINCTRL_PFC_R8A7794
 	depends on ARCH_R8A7794
 	select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7795
+	def_bool y
+	depends on ARCH_RCAR_GEN3
+	select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_SH7203
 	def_bool y
 	depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index ea2a60e..173305f 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7790)	+= pfc-r8a7790.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7791)	+= pfc-r8a7791.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7793)	+= pfc-r8a7791.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7794)	+= pfc-r8a7794.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7795)	+= pfc-r8a7795.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
 obj-$(CONFIG_PINCTRL_PFC_SH7264)	+= pfc-sh7264.o
 obj-$(CONFIG_PINCTRL_PFC_SH7269)	+= pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index fb9c448..bcf3017 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -489,6 +489,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
 		.data = &r8a7794_pinmux_info,
 	},
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
+	{
+		.compatible = "renesas,pfc-r8a7795",
+		.data = &r8a7795_pinmux_info,
+	},
+#endif
 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 	{
 		.compatible = "renesas,pfc-sh73a0",
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 4c3c37b..45398f6 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -73,6 +73,7 @@ extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
new file mode 100644
index 0000000..9437e87
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -0,0 +1,4299 @@
+/*
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015  Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx)						\
+	PORT_GP_32(0, fn, sfx),						\
+	PORT_GP_32(1, fn, sfx),						\
+	PORT_GP_32(2, fn, sfx),						\
+	PORT_GP_32(3, fn, sfx),						\
+	PORT_GP_32(4, fn, sfx),						\
+	PORT_GP_32(5, fn, sfx),						\
+	PORT_GP_32(6, fn, sfx),						\
+	PORT_GP_32(7, fn, sfx)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24,
+	FN_IP5_31_28, FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8,
+	FN_IP6_15_12, FN_IP6_19_16, FN_IP6_23_20, FN_IP6_27_24,
+	FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4, FN_IP7_11_8,
+
+	/* GPSR1 */
+	FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8,
+	FN_IP2_15_12, FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24,
+	FN_IP2_31_28, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+	FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20, FN_IP3_27_24,
+	FN_IP3_31_28, FN_IP4_3_0, FN_IP4_7_4, FN_IP4_11_8,
+	FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20, FN_IP4_27_24,
+	FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
+
+	/* GPSR2 */
+	FN_IP0_27_24, FN_IP0_31_28, FN_IP1_3_0, FN_IP1_7_4,
+	FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20,
+	FN_IP1_27_24, FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8,
+	FN_IP0_15_12, FN_IP0_19_16, FN_IP0_23_20,
+
+	/* GPSR3 */
+	FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24, FN_IP7_31_28,
+	FN_IP8_3_0, FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12,
+	FN_IP8_19_16, FN_IP8_23_20, FN_IP8_27_24, FN_IP8_31_28,
+	FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16, FN_IP10_23_20,
+
+	/* GPSR4 */
+	FN_IP9_3_0, FN_SD2_CMD_MMC0_CMD, FN_IP9_7_4, FN_IP9_11_8,
+	FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_SD3_CLK_MMC1_CLK,
+	FN_SD3_CMD_MMC1_CMD, FN_SD3_DAT0_MMC1_DAT0, FN_SD3_DAT1_MMC1_DAT1,
+	FN_SD3_DAT2_MMC1_DAT2, FN_SD3_DAT3_MMC1_DAT3,
+	FN_IP9_27_24, FN_IP9_31_28, FN_IP10_3_0, FN_IP10_7_4, FN_SD3_DS_MMC1_DS,
+
+	/* GPSR5 */
+	FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
+	FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
+	FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4,
+	FN_IP12_11_8, FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20,
+	FN_IP12_27_24, FN_MSIOF0_SCK, FN_IP12_31_28, FN_IP13_3_0,
+	FN_MSIOF0_TXD, FN_IP13_7_4, FN_MSIOF0_RXD, FN_IP13_11_8,
+	FN_IP13_15_12, FN_IP13_19_16,
+
+	/* GPSR6 */
+	FN_IP13_23_20, FN_IP13_27_24, FN_IP13_31_28, FN_IP14_3_0,
+	FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12, FN_IP14_19_16,
+	FN_IP14_23_20,	FN_IP14_27_24, FN_IP14_31_28, FN_SSI_SCK5,
+	FN_SSI_WS5, FN_SSI_SDATA5, FN_IP15_3_0, FN_IP15_7_4,
+	FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16, FN_IP15_23_20,
+	FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
+	FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
+	FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4,
+
+	/* GPSR7 */
+	FN_AVS1, FN_AVS2, FN_HDMI0_CEC, FN_HDMI1_CEC,
+
+	/* IPSR0 */
+	FN_AVB_MDC, FN_MSIOF2_SS2_C, FN_AVB_MAGIC, FN_MSIOF2_SS1_C,
+	FN_SCK4_A, FN_AVB_PHY_INT, FN_MSIOF2_SYNC_C, FN_RX4_A,
+	FN_AVB_LINK, FN_MSIOF2_SCK_C, FN_TX4_A, FN_AVB_AVTP_MATCH_A,
+	FN_MSIOF2_RXD_C, FN_CTS4_N_A, FN_AVB_AVTP_CAPTURE_A,
+	FN_MSIOF2_TXD_C, FN_RTS4_N_TANS_A, FN_IRQ0, FN_QPOLB,
+	FN_DU_CDE, FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B,
+	FN_IRQ1, FN_QPOLA, FN_DU_DISP, FN_VI4_DATA1_B, FN_CAN0_RX_B,
+	FN_CANFD0_RX_B,
+
+	/* IPSR1 */
+	FN_IRQ2, FN_QCPV_QDE, FN_DU_EXODDF_DU_ODDF_DISP_CDE,
+	FN_VI4_DATA2_B, FN_PWM3_B, FN_IRQ3, FN_QSTVB_QVE,
+	FN_DU_DOTCLKOUT1, FN_VI4_DATA3_B, FN_PWM4_B, FN_IRQ4,
+	FN_QSTH_QHS, FN_DU_EXHSYNC_DU_HSYNC, FN_VI4_DATA4_B, FN_PWM5_B,
+	FN_IRQ5, FN_QSTB_QHE, FN_DU_EXVSYNC_DU_VSYNC, FN_VI4_DATA5_B,
+	FN_PWM6_B, FN_PWM0, FN_AVB_AVTP_PPS, FN_VI4_DATA6_B,
+	FN_IECLK_B, FN_PWM1_A, FN_HRX3_D, FN_VI4_DATA7_B, FN_IERX_B,
+	FN_PWM2_A, FN_HTX3_D, FN_IETX_B, FN_A0, FN_LCDOUT16,
+	FN_MSIOF3_SYNC_B, FN_VI4_DATA8, FN_DU_DB0, FN_PWM3_A,
+
+	/* IPSR2 */
+	FN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, FN_VI4_DATA9, FN_DU_DB1,
+	FN_PWM4_A, FN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, FN_VI4_DATA10,
+	FN_DU_DB2, FN_PWM5_A, FN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B,
+	FN_VI4_DATA11, FN_DU_DB3, FN_PWM6_A, FN_A4, FN_LCDOUT20,
+	FN_MSIOF3_SS1_B, FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4,
+	FN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, FN_VI4_DATA13,
+	FN_VI5_DATA13, FN_DU_DB5, FN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A,
+	FN_RX4_B, FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, FN_A7,
+	FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, FN_VI4_DATA15,
+	FN_VI5_DATA15, FN_DU_DB7, FN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A,
+	FN_HRX4_B, FN_SDA6_A, FN_AVB_AVTP_MATCH_B, FN_PWM1_B,
+
+	/* IPSR3 */
+	FN_A9, FN_MSIOF2_SCK_A, FN_CTS4_N_B, FN_VI5_VSYNC_N, FN_A10,
+	FN_MSIOF2_RXD_A, FN_RTS4_N_TANS_B, FN_VI5_HSYNC_N, FN_A11,
+	FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, FN_HSCK4, FN_VI5_FIELD,
+	FN_SCL6_A, FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_A12,
+	FN_LCDOUT12, FN_MSIOF3_SCK_C, FN_HRX4_A, FN_VI5_DATA8,
+	FN_DU_DG4, FN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, FN_HTX4_A,
+	FN_VI5_DATA9, FN_DU_DG5, FN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C,
+	FN_HCTS4_N, FN_VI5_DATA10, FN_DU_DG6, FN_A15, FN_LCDOUT15,
+	FN_MSIOF3_TXD_C, FN_HRTS4_N, FN_VI5_DATA11, FN_DU_DG7, FN_A16,
+	FN_LCDOUT8, FN_VI4_FIELD, FN_DU_DG0,
+
+	/* IPSR4 */
+	FN_A17, FN_LCDOUT9, FN_VI4_VSYNC_N, FN_DU_DG1, FN_A18,
+	FN_LCDOUT10, FN_VI4_HSYNC_N, FN_DU_DG2, FN_A19, FN_LCDOUT11,
+	FN_VI4_CLKENB, FN_DU_DG3, FN_CS0_N, FN_VI5_CLKENB,
+	FN_CS1_N_A26, FN_VI5_CLK, FN_EX_WAIT0_B, FN_BS_N,
+	FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, FN_HSCK3, FN_CAN1_TX,
+	FN_CANFD1_TX, FN_IETX_A, FN_RD_N, FN_MSIOF3_SYNC_D, FN_RX3_A,
+	FN_HRX3_A, FN_CAN0_TX_A, FN_CANFD0_TX_A, FN_RD_WR_N,
+	FN_MSIOF3_RXD_D, FN_TX3_A, FN_HTX3_A, FN_CAN0_RX_A,
+	FN_CANFD0_RX_A,
+
+	/* IPSR5 */
+	FN_WE0_N, FN_MSIOF3_TXD_D, FN_CTS3_N, FN_HCTS3_N, FN_SCL6_B,
+	FN_CAN_CLK, FN_IECLK_A, FN_WE1_N, FN_MSIOF3_SS1_D,
+	FN_RTS3_N_TANS, FN_HRTS3_N, FN_SDA6_B, FN_CAN1_RX,
+	FN_CANFD1_RX, FN_IERX_A, FN_EX_WAIT0_A, FN_QCLK, FN_VI4_CLK,
+	FN_DU_DOTCLKOUT0, FN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A,
+	FN_VI4_DATA16, FN_VI5_DATA0, FN_D1, FN_MSIOF2_SS2_B,
+	FN_MSIOF3_SYNC_A, FN_VI4_DATA17, FN_VI5_DATA1, FN_D2,
+	FN_MSIOF3_RXD_A, FN_VI4_DATA18, FN_VI5_DATA2, FN_D3,
+	FN_MSIOF3_TXD_A, FN_VI4_DATA19, FN_VI5_DATA3, FN_D4,
+	FN_MSIOF2_SCK_B, FN_VI4_DATA20, FN_VI5_DATA4,
+
+	/* IPSR6 */
+	FN_D5, FN_MSIOF2_SYNC_B, FN_VI4_DATA21, FN_VI5_DATA5, FN_D6,
+	FN_MSIOF2_RXD_B, FN_VI4_DATA22, FN_VI5_DATA6, FN_D7,
+	FN_MSIOF2_TXD_B, FN_VI4_DATA23, FN_VI5_DATA7, FN_D8,
+	FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, FN_VI4_DATA0_A,
+	FN_DU_DR0, FN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D,
+	FN_VI4_DATA1_A, FN_DU_DR1, FN_D10, FN_LCDOUT2,
+	FN_MSIOF2_RXD_D, FN_HRX3_B, FN_VI4_DATA2_A, FN_CTS4_N_C,
+	FN_DU_DR2, FN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B,
+	FN_VI4_DATA3_A, FN_RTS4_N_TANS_C, FN_DU_DR3, FN_D12,
+	FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, FN_VI4_DATA4_A,
+	FN_DU_DR4,
+
+	/* IPSR7 */
+	FN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, FN_VI4_DATA5_A,
+	FN_DU_DR5, FN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C,
+	FN_VI4_DATA6_A, FN_DU_DR6, FN_SCL6_C, FN_D15, FN_LCDOUT7,
+	FN_MSIOF3_SS2_A, FN_HTX3_C, FN_VI4_DATA7_A, FN_DU_DR7,
+	FN_SDA6_C, FN_FSCLKST, FN_SD0_CLK, FN_MSIOF1_SCK_E,
+	FN_STP_OPWM_0_B, FN_SD0_CMD, FN_MSIOF1_SYNC_E,
+	FN_STP_IVCXO27_0_B, FN_SD0_DAT0, FN_MSIOF1_RXD_E, FN_TS_SCK0_B,
+	FN_STP_ISCLK_0_B, FN_SD0_DAT1, FN_MSIOF1_TXD_E, FN_TS_SPSYNC0_B,
+	FN_STP_ISSYNC_0_B,
+
+	/* IPSR8 */
+	FN_SD0_DAT2, FN_MSIOF1_SS1_E, FN_TS_SDAT0_B, FN_STP_ISD_0_B,
+	FN_SD0_DAT3, FN_MSIOF1_SS2_E, FN_TS_SDEN0_B, FN_STP_ISEN_0_B,
+	FN_SD1_CLK, FN_MSIOF1_SCK_G, FN_SIM0_CLK_A, FN_SD1_CMD,
+	FN_MSIOF1_SYNC_G, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, FN_SD1_DAT0,
+	FN_SD2_DAT4_MMC0_DAT4, FN_MSIOF1_RXD_G, FN_TS_SCK1_B,
+	FN_STP_ISCLK_1_B, FN_SD1_DAT1, FN_SD2_DAT5_MMC0_DAT5,
+	FN_MSIOF1_TXD_G, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B,
+	FN_SD1_DAT2, FN_SD2_DAT6_MMC0_DAT6, FN_MSIOF1_SS1_G,
+	FN_TS_SDAT1_B, FN_STP_ISD_1_B, FN_SD1_DAT3,
+	FN_SD2_DAT7_MMC0_DAT7, FN_MSIOF1_SS2_G, FN_TS_SDEN1_B,
+	FN_STP_ISEN_1_B,
+
+	/* IPSR9 */
+	FN_SD2_CLK_MMC0_CLK, FN_SD2_DAT0_MMC0_DAT0, FN_SD2_DAT1_MMC0_DAT1,
+	FN_SD2_DAT2_MMC0_DAT2, FN_SD2_DAT3_MMC0_DAT3, FN_SD2_DS_MMC0_DS,
+	FN_SATA_DEVSLP_B, FN_SD3_DAT4_MMC1_DAT4, FN_SD2_CD_A,
+	FN_SD3_DAT5_MMC1_DAT5, FN_SD2_WP_A,
+
+	/* IPSR10 */
+	FN_SD3_DAT6_MMC1_DAT6, FN_SD3_CD, FN_SD3_DAT7_MMC1_DAT7,
+	FN_SD3_WP, FN_SD0_CD, FN_SCL2_B, FN_SIM0_RST_A, FN_SD0_WP,
+	FN_SDA2_B, FN_SD1_CD, FN_SIM0_CLK_B, FN_SD1_WP, FN_SIM0_D_B,
+	FN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,
+	FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B,
+	FN_ADICHS2, FN_RX0, FN_HRX1_B, FN_TS_SCK0_C, FN_STP_ISCLK_0_C,
+	FN_RIF0_D0_B,
+
+	/* IPSR11 */
+	FN_TX0, FN_HTX1_B, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C,
+	FN_RIF0_D1_B, FN_CTS0_N, FN_HCTS1_N_B, FN_MSIOF1_SYNC_B,
+	FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,
+	FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, FN_RTS0_N_TANS, FN_HRTS1_N_B,
+	FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, FN_SCL2_A, FN_STP_IVCXO27_1_C,
+	FN_RIF0_SYNC_B, FN_ADICHS1, FN_RX1_A, FN_HRX1_A,
+	FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, FN_TX1_A,
+	FN_HTX1_A, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,
+	FN_CTS1_N, FN_HCTS1_N_A, FN_MSIOF1_RXD_B, FN_TS_SDEN1_C,
+	FN_STP_ISEN_1_C, FN_RIF1_D0_B, FN_ADIDATA, FN_RTS1_N_TANS,
+	FN_HRTS1_N_A, FN_MSIOF1_TXD_B, FN_TS_SDAT1_C, FN_STP_ISD_1_C,
+	FN_RIF1_D1_B, FN_ADICHS0, FN_SCK2, FN_SCIF_CLK_B,
+	FN_MSIOF1_SCK_B, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,
+	FN_ADICLK,
+
+	/* IPSR12 */
+	FN_TX2_A, FN_SD2_CD_B, FN_SCL1_A, FN_FMCLK_A, FN_RIF1_D1_C,
+	FN_FSO_CFE_0_B, FN_RX2_A, FN_SD2_WP_B, FN_SDA1_A, FN_FMIN_A,
+	FN_RIF1_SYNC_C, FN_FSO_CFE_1_B, FN_HSCK0, FN_MSIOF1_SCK_D,
+	FN_AUDIO_CLKB_A, FN_SSI_SDATA1_B, FN_TS_SCK0_D,
+	FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, FN_HRX0, FN_MSIOF1_RXD_D,
+	FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,
+	FN_HTX0, FN_MSIOF1_TXD_D, FN_SSI_SDATA9_B, FN_TS_SDAT0_D,
+	FN_STP_ISD_0_D, FN_RIF0_D1_C, FN_HCTS0_N, FN_RX2_B,
+	FN_MSIOF1_SYNC_D, FN_SSI_SCK9_A, FN_TS_SPSYNC0_D,
+	FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C, FN_AUDIO_CLKOUT1_A,
+	FN_HRTS0_N, FN_TX2_B, FN_MSIOF1_SS1_D, FN_SSI_WS9_A,
+	FN_STP_IVCXO27_0_D, FN_BPFCLK_A, FN_AUDIO_CLKOUT2_A,
+	FN_MSIOF0_SYNC, FN_AUDIO_CLKOUT_A,
+
+	/* IPSR13 */
+	FN_MSIOF0_SS1, FN_RX5, FN_AUDIO_CLKA_C, FN_SSI_SCK2_A,
+	FN_STP_IVCXO27_0_C, FN_AUDIO_CLKOUT3_A, FN_TCLK1_B,
+	FN_MSIOF0_SS2, FN_TX5, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,
+	FN_SSI_WS2_A, FN_STP_OPWM_0_D, FN_AUDIO_CLKOUT_D, FN_SPEEDIN_B,
+	FN_MLB_CLK, FN_MSIOF1_SCK_F, FN_SCL1_B, FN_MLB_SIG, FN_RX1_B,
+	FN_MSIOF1_SYNC_F, FN_SDA1_B, FN_MLB_DAT, FN_TX1_B,
+	FN_MSIOF1_RXD_F, FN_SSI_SCK0129, FN_MSIOF1_TXD_F, FN_SSI_WS0129,
+	FN_MSIOF1_SS1_F, FN_SSI_SDATA0, FN_MSIOF1_SS2_F,
+
+	/* IPSR14 */
+	FN_SSI_SDATA1_A, FN_SSI_SDATA2_A, FN_SSI_SCK1_B, FN_SSI_SCK34,
+	FN_MSIOF1_SS1_A, FN_STP_OPWM_0_A, FN_SSI_WS34, FN_HCTS2_N_A,
+	FN_MSIOF1_SS2_A, FN_STP_IVCXO27_0_A, FN_SSI_SDATA3,
+	FN_HRTS2_N_A, FN_MSIOF1_TXD_A, FN_TS_SCK0_A, FN_STP_ISCLK_0_A,
+	FN_RIF0_D1_A, FN_RIF2_D0_A, FN_SSI_SCK4, FN_HRX2_A,
+	FN_MSIOF1_SCK_A, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,
+	FN_RIF2_CLK_A, FN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A,
+	FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, FN_RIF2_SYNC_A,
+	FN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, FN_TS_SPSYNC0_A,
+	FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, FN_RIF2_D1_A,
+
+	/* IPSR15 */
+	FN_SSI_SCK6, FN_USB2_PWEN, FN_SIM0_RST_D, FN_SSI_WS6,
+	FN_USB2_OVC, FN_SIM0_D_D, FN_SSI_SDATA6, FN_SIM0_CLK_D,
+	FN_SATA_DEVSLP_A, FN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C,
+	FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, FN_RIF3_CLK_A,
+	FN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, FN_TS_SDAT1_A,
+	FN_STP_ISD_1_A, FN_RIF1_SYNC_A, FN_RIF3_SYNC_A, FN_SSI_SDATA7,
+	FN_HCTS2_N_B, FN_MSIOF1_RXD_C, FN_TS_SDEN1_A, FN_STP_ISEN_1_A,
+	FN_RIF1_D0_A, FN_RIF3_D0_A, FN_TCLK2_A, FN_SSI_SDATA8,
+	FN_HRTS2_N_B, FN_MSIOF1_TXD_C, FN_TS_SPSYNC1_A,
+	FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, FN_RIF3_D1_A, FN_SSI_SDATA9_A,
+	FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, FN_SSI_WS1_B,
+	FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5,
+
+	/* IPSR16 */
+	FN_AUDIO_CLKA_A, FN_CC5_OSCOUT, FN_AUDIO_CLKB_B, FN_SCIF_CLK_A,
+	FN_STP_IVCXO27_1_D, FN_REMOCON_A, FN_TCLK1_A, FN_USB0_PWEN,
+	FN_SIM0_RST_C, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,
+	FN_RIF3_CLK_B, FN_USB0_OVC, FN_SIM0_D_C, FN_TS_SDAT1_D,
+	FN_STP_ISD_1_D, FN_RIF3_SYNC_B, FN_USB1_PWEN, FN_SIM0_CLK_C,
+	FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,
+	FN_RIF2_CLK_B, FN_SPEEDIN_A, FN_USB1_OVC, FN_MSIOF1_SS2_C,
+	FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,
+	FN_RIF2_SYNC_B, FN_REMOCON_B, FN_USB30_PWEN, FN_AUDIO_CLKOUT_B,
+	FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,
+	FN_RIF3_D0_B, FN_TCLK2_B, FN_TPU0TO0, FN_USB30_OVC,
+	FN_AUDIO_CLKOUT1_B, FN_SSI_WS2_B, FN_TS_SPSYNC1_D,
+	FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E, FN_RIF3_D1_B,
+	FN_FSO_TOE_B, FN_TPU0TO1,
+
+	/* IPSR17 */
+	FN_USB31_PWEN, FN_AUDIO_CLKOUT2_B, FN_SSI_SCK9_B, FN_TS_SDEN0_E,
+	FN_STP_ISEN_0_E, FN_RIF2_D0_B, FN_TPU0TO2, FN_USB31_OVC,
+	FN_AUDIO_CLKOUT3_B, FN_SSI_WS9_B, FN_TS_SPSYNC0_E,
+	FN_STP_ISSYNC_0_E, FN_RIF2_D1_B, FN_TPU0TO3,
+
+	/* MOD_SEL0 */
+	FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, FN_SEL_CANFD0_0,
+	FN_SEL_CANFD0_1, FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, FN_SEL_DRIF0_2,
+	FN_SEL_DRIF0_3, FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, FN_SEL_DRIF1_2,
+	FN_SEL_DRIF1_3, FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, FN_SEL_DRIF3_0,
+	FN_SEL_DRIF3_1, FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, FN_SEL_FM_0,
+	FN_SEL_FM_1, FN_SEL_FSO_0, FN_SEL_FSO_1, FN_SEL_HSCIF1_0,
+	FN_SEL_HSCIF1_1, FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF3_0,
+	FN_SEL_HSCIF3_1, FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, FN_SEL_HSCIF4_0,
+	FN_SEL_HSCIF4_1, FN_SEL_I2C1_0, FN_SEL_I2C1_1,
+	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C6_0, FN_SEL_I2C6_1,
+	FN_SEL_I2C6_2, FN_SEL_I2C6_3, FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
+	FN_SEL_LBSC_0, FN_SEL_LBSC_1, FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
+	FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, FN_SEL_MSIOF1_4,
+	FN_SEL_MSIOF1_5, FN_SEL_MSIOF1_6, FN_SEL_MSIOF1_7,
+	FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
+	FN_SEL_MSIOF2_3, FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
+	FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
+
+	/* MOD_SEL1 */
+	FN_SEL_PWM1_0, FN_SEL_PWM1_1, FN_SEL_PWM2_0, FN_SEL_PWM2_1,
+	FN_SEL_PWM3_0, FN_SEL_PWM3_1, FN_SEL_PWM4_0, FN_SEL_PWM4_1,
+	FN_SEL_PWM5_0, FN_SEL_PWM5_1, FN_SEL_PWM6_0, FN_SEL_PWM6_1,
+	FN_SEL_RCAN0_0, FN_SEL_RCAN0_1, FN_SEL_REMOCON_0, FN_SEL_REMOCON_1,
+	FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
+	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+	FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, FN_SEL_SIMCARD_0,
+	FN_SEL_SIMCARD_1, FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,
+	FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,
+	FN_SEL_SSI_0, FN_SEL_SSI_1, FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,
+	FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, FN_SEL_SSP1_0_4,
+	FN_SEL_SSP1_0_5, FN_SEL_SSP1_0_6, FN_SEL_SSP1_0_7,
+	FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, FN_SEL_SSP1_1_2,
+	FN_SEL_SSP1_1_3, FN_SEL_TIMER_TMU_0, FN_SEL_TIMER_TMU_1,
+	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+	FN_SEL_TSIF0_4, FN_SEL_TSIF0_5, FN_SEL_TSIF0_6, FN_SEL_TSIF0_7,
+	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, FN_SEL_TSIF1_3,
+
+	/* MOD_SEL2 */
+	FN_SEL_VIN4_0, FN_SEL_VIN4_1, FN_SEL_VSP_0, FN_SEL_VSP_1,
+	FN_SEL_VSP_2, FN_SEL_VSP_3, FN_I2C_SEL_0_0, FN_I2C_SEL_0_1,
+	FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, FN_I2C_SEL_5_0, FN_I2C_SEL_5_1,
+
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	/* GPSR0 */
+	IP5_15_12_MARK, IP5_19_16_MARK, IP5_23_20_MARK, IP5_27_24_MARK,
+	IP5_31_28_MARK, IP6_3_0_MARK, IP6_7_4_MARK, IP6_11_8_MARK,
+	IP6_15_12_MARK, IP6_19_16_MARK, IP6_23_20_MARK, IP6_27_24_MARK,
+	IP6_31_28_MARK, IP7_3_0_MARK, IP7_7_4_MARK, IP7_11_8_MARK,
+
+	/* GPSR1 */
+	IP1_31_28_MARK, IP2_3_0_MARK, IP2_7_4_MARK, IP2_11_8_MARK,
+	IP2_15_12_MARK, IP2_19_16_MARK, IP2_23_20_MARK, IP2_27_24_MARK,
+	IP2_31_28_MARK, IP3_3_0_MARK, IP3_7_4_MARK, IP3_11_8_MARK,
+	IP3_15_12_MARK, IP3_19_16_MARK, IP3_23_20_MARK, IP3_27_24_MARK,
+	IP3_31_28_MARK, IP4_3_0_MARK, IP4_7_4_MARK, IP4_11_8_MARK,
+	IP4_15_12_MARK, IP4_19_16_MARK, IP4_23_20_MARK, IP4_27_24_MARK,
+	IP4_31_28_MARK, IP5_3_0_MARK, IP5_7_4_MARK, IP5_11_8_MARK,
+
+	/* GPSR2 */
+	IP0_27_24_MARK, IP0_31_28_MARK, IP1_3_0_MARK, IP1_7_4_MARK,
+	IP1_11_8_MARK, IP1_15_12_MARK, IP1_19_16_MARK, IP1_23_20_MARK,
+	IP1_27_24_MARK, IP0_3_0_MARK, IP0_7_4_MARK, IP0_11_8_MARK,
+	IP0_15_12_MARK, IP0_19_16_MARK, IP0_23_20_MARK,
+
+	/* GPSR3 */
+	IP7_19_16_MARK, IP7_23_20_MARK, IP7_27_24_MARK, IP7_31_28_MARK,
+	IP8_3_0_MARK, IP8_7_4_MARK, IP8_11_8_MARK, IP8_15_12_MARK,
+	IP8_19_16_MARK, IP8_23_20_MARK, IP8_27_24_MARK, IP8_31_28_MARK,
+	IP10_11_8_MARK, IP10_15_12_MARK, IP10_19_16_MARK, IP10_23_20_MARK,
+
+	/* GPSR4 */
+	IP9_3_0_MARK, SD2_CMD_MMC0_CMD_MARK, IP9_7_4_MARK, IP9_11_8_MARK,
+	IP9_15_12_MARK, IP9_19_16_MARK, IP9_23_20_MARK, SD3_CLK_MMC1_CLK_MARK,
+	SD3_CMD_MMC1_CMD_MARK, SD3_DAT0_MMC1_DAT0_MARK, SD3_DAT1_MMC1_DAT1_MARK,
+	SD3_DAT2_MMC1_DAT2_MARK, SD3_DAT3_MMC1_DAT3_MARK, IP9_27_24_MARK,
+	IP9_31_28_MARK, IP10_3_0_MARK, IP10_7_4_MARK, SD3_DS_MMC1_DS_MARK,
+
+	/* GPSR5 */
+	IP10_27_24_MARK, IP10_31_28_MARK, IP11_3_0_MARK, IP11_7_4_MARK,
+	IP11_11_8_MARK, IP11_15_12_MARK, IP11_19_16_MARK, IP11_23_20_MARK,
+	IP11_27_24_MARK, IP11_31_28_MARK, IP12_3_0_MARK,  IP12_7_4_MARK,
+	IP12_11_8_MARK, IP12_15_12_MARK, IP12_19_16_MARK,  IP12_23_20_MARK,
+	IP12_27_24_MARK, MSIOF0_SCK_MARK, IP12_31_28_MARK, IP13_3_0_MARK,
+	MSIOF0_TXD_MARK, IP13_7_4_MARK, MSIOF0_RXD_MARK, IP13_11_8_MARK,
+	IP13_15_12_MARK, IP13_19_16_MARK,
+
+	/* GPSR6 */
+	IP13_23_20_MARK, IP13_27_24_MARK, IP13_31_28_MARK, IP14_3_0_MARK,
+	IP14_7_4_MARK, IP14_11_8_MARK, IP14_15_12_MARK, IP14_19_16_MARK,
+	IP14_23_20_MARK,  IP14_27_24_MARK, IP14_31_28_MARK, SSI_SCK5_MARK,
+	SSI_WS5_MARK, SSI_SDATA5_MARK, IP15_3_0_MARK, IP15_7_4_MARK,
+	IP15_11_8_MARK, IP15_15_12_MARK, IP15_19_16_MARK, IP15_23_20_MARK,
+	IP15_27_24_MARK, IP15_31_28_MARK, IP16_3_0_MARK, IP16_7_4_MARK,
+	IP16_11_8_MARK, IP16_15_12_MARK, IP16_19_16_MARK, IP16_23_20_MARK,
+	IP16_27_24_MARK, IP16_31_28_MARK, IP17_3_0_MARK, IP17_7_4_MARK,
+
+	/* GPSR7 */
+	AVS1_MARK, AVS2_MARK, HDMI0_CEC_MARK, HDMI1_CEC_MARK,
+
+	/* IPSR0 */
+	AVB_MDC_MARK, MSIOF2_SS2_C_MARK, AVB_MAGIC_MARK, MSIOF2_SS1_C_MARK,
+	SCK4_A_MARK, AVB_PHY_INT_MARK, MSIOF2_SYNC_C_MARK, RX4_A_MARK,
+	AVB_LINK_MARK, MSIOF2_SCK_C_MARK, TX4_A_MARK, AVB_AVTP_MATCH_A_MARK,
+	MSIOF2_RXD_C_MARK, CTS4_N_A_MARK, AVB_AVTP_CAPTURE_A_MARK,
+	MSIOF2_TXD_C_MARK, RTS4_N_TANS_A_MARK, IRQ0_MARK, QPOLB_MARK,
+	DU_CDE_MARK, VI4_DATA0_B_MARK, CAN0_TX_B_MARK, CANFD0_TX_B_MARK,
+	IRQ1_MARK, QPOLA_MARK, DU_DISP_MARK, VI4_DATA1_B_MARK, CAN0_RX_B_MARK,
+	CANFD0_RX_B_MARK,
+
+	/* IPSR1 */
+	IRQ2_MARK, QCPV_QDE_MARK, DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+	VI4_DATA2_B_MARK, PWM3_B_MARK, IRQ3_MARK, QSTVB_QVE_MARK,
+	DU_DOTCLKOUT1_MARK, VI4_DATA3_B_MARK, PWM4_B_MARK, IRQ4_MARK,
+	QSTH_QHS_MARK, DU_EXHSYNC_DU_HSYNC_MARK, VI4_DATA4_B_MARK, PWM5_B_MARK,
+	IRQ5_MARK, QSTB_QHE_MARK, DU_EXVSYNC_DU_VSYNC_MARK, VI4_DATA5_B_MARK,
+	PWM6_B_MARK, PWM0_MARK, AVB_AVTP_PPS_MARK, VI4_DATA6_B_MARK,
+	IECLK_B_MARK, PWM1_A_MARK, HRX3_D_MARK, VI4_DATA7_B_MARK, IERX_B_MARK,
+	PWM2_A_MARK, HTX3_D_MARK, IETX_B_MARK, A0_MARK, LCDOUT16_MARK,
+	MSIOF3_SYNC_B_MARK, VI4_DATA8_MARK, DU_DB0_MARK, PWM3_A_MARK,
+
+	/* IPSR2 */
+	A1_MARK, LCDOUT17_MARK, MSIOF3_TXD_B_MARK, VI4_DATA9_MARK, DU_DB1_MARK,
+	PWM4_A_MARK, A2_MARK, LCDOUT18_MARK, MSIOF3_SCK_B_MARK, VI4_DATA10_MARK,
+	DU_DB2_MARK, PWM5_A_MARK, A3_MARK, LCDOUT19_MARK, MSIOF3_RXD_B_MARK,
+	VI4_DATA11_MARK, DU_DB3_MARK, PWM6_A_MARK, A4_MARK, LCDOUT20_MARK,
+	MSIOF3_SS1_B_MARK, VI4_DATA12_MARK, VI5_DATA12_MARK, DU_DB4_MARK,
+	A5_MARK, LCDOUT21_MARK, MSIOF3_SS2_B_MARK, SCK4_B_MARK, VI4_DATA13_MARK,
+	VI5_DATA13_MARK, DU_DB5_MARK, A6_MARK, LCDOUT22_MARK, MSIOF2_SS1_A_MARK,
+	RX4_B_MARK, VI4_DATA14_MARK, VI5_DATA14_MARK, DU_DB6_MARK, A7_MARK,
+	LCDOUT23_MARK, MSIOF2_SS2_A_MARK, TX4_B_MARK, VI4_DATA15_MARK,
+	VI5_DATA15_MARK, DU_DB7_MARK, A8_MARK, RX3_B_MARK, MSIOF2_SYNC_A_MARK,
+	HRX4_B_MARK, SDA6_A_MARK, AVB_AVTP_MATCH_B_MARK, PWM1_B_MARK,
+
+	/* IPSR3 */
+	A9_MARK, MSIOF2_SCK_A_MARK, CTS4_N_B_MARK, VI5_VSYNC_N_MARK, A10_MARK,
+	MSIOF2_RXD_A_MARK, RTS4_N_TANS_B_MARK, VI5_HSYNC_N_MARK, A11_MARK,
+	TX3_B_MARK, MSIOF2_TXD_A_MARK, HTX4_B_MARK, HSCK4_MARK, VI5_FIELD_MARK,
+	SCL6_A_MARK, AVB_AVTP_CAPTURE_B_MARK, PWM2_B_MARK, A12_MARK,
+	LCDOUT12_MARK, MSIOF3_SCK_C_MARK, HRX4_A_MARK, VI5_DATA8_MARK,
+	DU_DG4_MARK, A13_MARK, LCDOUT13_MARK, MSIOF3_SYNC_C_MARK, HTX4_A_MARK,
+	VI5_DATA9_MARK, DU_DG5_MARK, A14_MARK, LCDOUT14_MARK, MSIOF3_RXD_C_MARK,
+	HCTS4_N_MARK, VI5_DATA10_MARK, DU_DG6_MARK, A15_MARK, LCDOUT15_MARK,
+	MSIOF3_TXD_C_MARK, HRTS4_N_MARK, VI5_DATA11_MARK, DU_DG7_MARK, A16_MARK,
+	LCDOUT8_MARK, VI4_FIELD_MARK, DU_DG0_MARK,
+
+	/* IPSR4 */
+	A17_MARK, LCDOUT9_MARK, VI4_VSYNC_N_MARK, DU_DG1_MARK, A18_MARK,
+	LCDOUT10_MARK, VI4_HSYNC_N_MARK, DU_DG2_MARK, A19_MARK, LCDOUT11_MARK,
+	VI4_CLKENB_MARK, DU_DG3_MARK, CS0_N_MARK, VI5_CLKENB_MARK,
+	CS1_N_A26_MARK, VI5_CLK_MARK, EX_WAIT0_B_MARK, BS_N_MARK,
+	QSTVA_QVS_MARK, MSIOF3_SCK_D_MARK, SCK3_MARK, HSCK3_MARK, CAN1_TX_MARK,
+	CANFD1_TX_MARK, IETX_A_MARK, RD_N_MARK, MSIOF3_SYNC_D_MARK, RX3_A_MARK,
+	HRX3_A_MARK, CAN0_TX_A_MARK, CANFD0_TX_A_MARK, RD_WR_N_MARK,
+	MSIOF3_RXD_D_MARK, TX3_A_MARK, HTX3_A_MARK, CAN0_RX_A_MARK,
+	CANFD0_RX_A_MARK,
+
+	/* IPSR5 */
+	WE0_N_MARK, MSIOF3_TXD_D_MARK, CTS3_N_MARK, HCTS3_N_MARK, SCL6_B_MARK,
+	CAN_CLK_MARK, IECLK_A_MARK, WE1_N_MARK, MSIOF3_SS1_D_MARK,
+	RTS3_N_TANS_MARK, HRTS3_N_MARK, SDA6_B_MARK, CAN1_RX_MARK,
+	CANFD1_RX_MARK, IERX_A_MARK, EX_WAIT0_A_MARK, QCLK_MARK, VI4_CLK_MARK,
+	DU_DOTCLKOUT0_MARK, D0_MARK, MSIOF2_SS1_B_MARK, MSIOF3_SCK_A_MARK,
+	VI4_DATA16_MARK, VI5_DATA0_MARK, D1_MARK, MSIOF2_SS2_B_MARK,
+	MSIOF3_SYNC_A_MARK, VI4_DATA17_MARK, VI5_DATA1_MARK, D2_MARK,
+	MSIOF3_RXD_A_MARK, VI4_DATA18_MARK, VI5_DATA2_MARK, D3_MARK,
+	MSIOF3_TXD_A_MARK, VI4_DATA19_MARK, VI5_DATA3_MARK, D4_MARK,
+	MSIOF2_SCK_B_MARK, VI4_DATA20_MARK, VI5_DATA4_MARK,
+
+	/* IPSR6 */
+	D5_MARK, MSIOF2_SYNC_B_MARK, VI4_DATA21_MARK, VI5_DATA5_MARK, D6_MARK,
+	MSIOF2_RXD_B_MARK, VI4_DATA22_MARK, VI5_DATA6_MARK, D7_MARK,
+	MSIOF2_TXD_B_MARK, VI4_DATA23_MARK, VI5_DATA7_MARK, D8_MARK,
+	LCDOUT0_MARK, MSIOF2_SCK_D_MARK, SCK4_C_MARK, VI4_DATA0_A_MARK,
+	DU_DR0_MARK, D9_MARK, LCDOUT1_MARK, MSIOF2_SYNC_D_MARK,
+	VI4_DATA1_A_MARK, DU_DR1_MARK, D10_MARK, LCDOUT2_MARK,
+	MSIOF2_RXD_D_MARK, HRX3_B_MARK, VI4_DATA2_A_MARK, CTS4_N_C_MARK,
+	DU_DR2_MARK, D11_MARK, LCDOUT3_MARK, MSIOF2_TXD_D_MARK, HTX3_B_MARK,
+	VI4_DATA3_A_MARK, RTS4_N_TANS_C_MARK, DU_DR3_MARK, D12_MARK,
+	LCDOUT4_MARK, MSIOF2_SS1_D_MARK, RX4_C_MARK, VI4_DATA4_A_MARK,
+	DU_DR4_MARK,
+
+	/* IPSR7 */
+	D13_MARK, LCDOUT5_MARK, MSIOF2_SS2_D_MARK, TX4_C_MARK, VI4_DATA5_A_MARK,
+	DU_DR5_MARK, D14_MARK, LCDOUT6_MARK, MSIOF3_SS1_A_MARK, HRX3_C_MARK,
+	VI4_DATA6_A_MARK, DU_DR6_MARK, SCL6_C_MARK, D15_MARK, LCDOUT7_MARK,
+	MSIOF3_SS2_A_MARK, HTX3_C_MARK, VI4_DATA7_A_MARK, DU_DR7_MARK,
+	SDA6_C_MARK, FSCLKST_MARK, SD0_CLK_MARK, MSIOF1_SCK_E_MARK,
+	STP_OPWM_0_B_MARK, SD0_CMD_MARK, MSIOF1_SYNC_E_MARK,
+	STP_IVCXO27_0_B_MARK, SD0_DAT0_MARK, MSIOF1_RXD_E_MARK, TS_SCK0_B_MARK,
+	STP_ISCLK_0_B_MARK, SD0_DAT1_MARK, MSIOF1_TXD_E_MARK, TS_SPSYNC0_B_MARK,
+	STP_ISSYNC_0_B_MARK,
+
+	/* IPSR8 */
+	SD0_DAT2_MARK, MSIOF1_SS1_E_MARK, TS_SDAT0_B_MARK, STP_ISD_0_B_MARK,
+	SD0_DAT3_MARK, MSIOF1_SS2_E_MARK, TS_SDEN0_B_MARK, STP_ISEN_0_B_MARK,
+	SD1_CLK_MARK, MSIOF1_SCK_G_MARK, SIM0_CLK_A_MARK, SD1_CMD_MARK,
+	MSIOF1_SYNC_G_MARK, SIM0_D_A_MARK, STP_IVCXO27_1_B_MARK, SD1_DAT0_MARK,
+	SD2_DAT4_MMC0_DAT4_MARK, MSIOF1_RXD_G_MARK, TS_SCK1_B_MARK,
+	STP_ISCLK_1_B_MARK, SD1_DAT1_MARK, SD2_DAT5_MMC0_DAT5_MARK,
+	MSIOF1_TXD_G_MARK, TS_SPSYNC1_B_MARK, STP_ISSYNC_1_B_MARK,
+	SD1_DAT2_MARK, SD2_DAT6_MMC0_DAT6_MARK, MSIOF1_SS1_G_MARK,
+	TS_SDAT1_B_MARK, STP_ISD_1_B_MARK, SD1_DAT3_MARK,
+	SD2_DAT7_MMC0_DAT7_MARK, MSIOF1_SS2_G_MARK, TS_SDEN1_B_MARK,
+	STP_ISEN_1_B_MARK,
+
+	/* IPSR9 */
+	SD2_CLK_MMC0_CLK_MARK, SD2_DAT0_MMC0_DAT0_MARK, SD2_DAT1_MMC0_DAT1_MARK,
+	SD2_DAT2_MMC0_DAT2_MARK, SD2_DAT3_MMC0_DAT3_MARK, SD2_DS_MMC0_DS_MARK,
+	SATA_DEVSLP_B_MARK, SD3_DAT4_MMC1_DAT4_MARK, SD2_CD_A_MARK,
+	SD3_DAT5_MMC1_DAT5_MARK, SD2_WP_A_MARK,
+
+	/* IPSR10 */
+	SD3_DAT6_MMC1_DAT6_MARK, SD3_CD_MARK, SD3_DAT7_MMC1_DAT7_MARK,
+	SD3_WP_MARK, SD0_CD_MARK, SCL2_B_MARK, SIM0_RST_A_MARK, SD0_WP_MARK,
+	SDA2_B_MARK, SD1_CD_MARK, SIM0_CLK_B_MARK, SD1_WP_MARK, SIM0_D_B_MARK,
+	SCK0_MARK, HSCK1_B_MARK, MSIOF1_SS2_B_MARK, AUDIO_CLKC_B_MARK,
+	SDA2_A_MARK, SIM0_RST_B_MARK, STP_OPWM_0_C_MARK, RIF0_CLK_B_MARK,
+	ADICHS2_MARK, RX0_MARK, HRX1_B_MARK, TS_SCK0_C_MARK, STP_ISCLK_0_C_MARK,
+	RIF0_D0_B_MARK,
+
+	/* IPSR11 */
+	TX0_MARK, HTX1_B_MARK, TS_SPSYNC0_C_MARK, STP_ISSYNC_0_C_MARK,
+	RIF0_D1_B_MARK, CTS0_N_MARK, HCTS1_N_B_MARK, MSIOF1_SYNC_B_MARK,
+	TS_SPSYNC1_C_MARK, STP_ISSYNC_1_C_MARK, RIF1_SYNC_B_MARK,
+	AUDIO_CLKOUT_C_MARK, ADICS_SAMP_MARK, RTS0_N_TANS_MARK, HRTS1_N_B_MARK,
+	MSIOF1_SS1_B_MARK, AUDIO_CLKA_B_MARK, SCL2_A_MARK, STP_IVCXO27_1_C_MARK,
+	RIF0_SYNC_B_MARK, ADICHS1_MARK, RX1_A_MARK, HRX1_A_MARK,
+	TS_SDAT0_C_MARK, STP_ISD_0_C_MARK, RIF1_CLK_C_MARK, TX1_A_MARK,
+	HTX1_A_MARK, TS_SDEN0_C_MARK, STP_ISEN_0_C_MARK, RIF1_D0_C_MARK,
+	CTS1_N_MARK, HCTS1_N_A_MARK, MSIOF1_RXD_B_MARK, TS_SDEN1_C_MARK,
+	STP_ISEN_1_C_MARK, RIF1_D0_B_MARK, ADIDATA_MARK, RTS1_N_TANS_MARK,
+	HRTS1_N_A_MARK, MSIOF1_TXD_B_MARK, TS_SDAT1_C_MARK, STP_ISD_1_C_MARK,
+	RIF1_D1_B_MARK, ADICHS0_MARK, SCK2_MARK, SCIF_CLK_B_MARK,
+	MSIOF1_SCK_B_MARK, TS_SCK1_C_MARK, STP_ISCLK_1_C_MARK, RIF1_CLK_B_MARK,
+	ADICLK_MARK,
+
+	/* IPSR12 */
+	TX2_A_MARK, SD2_CD_B_MARK, SCL1_A_MARK, FMCLK_A_MARK, RIF1_D1_C_MARK,
+	FSO_CFE_0_B_MARK, RX2_A_MARK, SD2_WP_B_MARK, SDA1_A_MARK, FMIN_A_MARK,
+	RIF1_SYNC_C_MARK, FSO_CFE_1_B_MARK, HSCK0_MARK, MSIOF1_SCK_D_MARK,
+	AUDIO_CLKB_A_MARK, SSI_SDATA1_B_MARK, TS_SCK0_D_MARK,
+	STP_ISCLK_0_D_MARK, RIF0_CLK_C_MARK, HRX0_MARK, MSIOF1_RXD_D_MARK,
+	SSI_SDATA2_B_MARK, TS_SDEN0_D_MARK, STP_ISEN_0_D_MARK, RIF0_D0_C_MARK,
+	HTX0_MARK, MSIOF1_TXD_D_MARK, SSI_SDATA9_B_MARK, TS_SDAT0_D_MARK,
+	STP_ISD_0_D_MARK, RIF0_D1_C_MARK, HCTS0_N_MARK, RX2_B_MARK,
+	MSIOF1_SYNC_D_MARK, SSI_SCK9_A_MARK, TS_SPSYNC0_D_MARK,
+	STP_ISSYNC_0_D_MARK, RIF0_SYNC_C_MARK, AUDIO_CLKOUT1_A_MARK,
+	HRTS0_N_MARK, TX2_B_MARK, MSIOF1_SS1_D_MARK, SSI_WS9_A_MARK,
+	STP_IVCXO27_0_D_MARK, BPFCLK_A_MARK, AUDIO_CLKOUT2_A_MARK,
+	MSIOF0_SYNC_MARK, AUDIO_CLKOUT_A_MARK,
+
+	/* IPSR13 */
+	MSIOF0_SS1_MARK, RX5_MARK, AUDIO_CLKA_C_MARK, SSI_SCK2_A_MARK,
+	STP_IVCXO27_0_C_MARK, AUDIO_CLKOUT3_A_MARK, TCLK1_B_MARK,
+	MSIOF0_SS2_MARK, TX5_MARK, MSIOF1_SS2_D_MARK, AUDIO_CLKC_A_MARK,
+	SSI_WS2_A_MARK, STP_OPWM_0_D_MARK, AUDIO_CLKOUT_D_MARK, SPEEDIN_B_MARK,
+	MLB_CLK_MARK, MSIOF1_SCK_F_MARK, SCL1_B_MARK, MLB_SIG_MARK, RX1_B_MARK,
+	MSIOF1_SYNC_F_MARK, SDA1_B_MARK, MLB_DAT_MARK, TX1_B_MARK,
+	MSIOF1_RXD_F_MARK, SSI_SCK0129_MARK, MSIOF1_TXD_F_MARK, SSI_WS0129_MARK,
+	MSIOF1_SS1_F_MARK, SSI_SDATA0_MARK, MSIOF1_SS2_F_MARK,
+
+	/* IPSR14 */
+	SSI_SDATA1_A_MARK, SSI_SDATA2_A_MARK, SSI_SCK1_B_MARK, SSI_SCK34_MARK,
+	MSIOF1_SS1_A_MARK, STP_OPWM_0_A_MARK, SSI_WS34_MARK, HCTS2_N_A_MARK,
+	MSIOF1_SS2_A_MARK, STP_IVCXO27_0_A_MARK, SSI_SDATA3_MARK,
+	HRTS2_N_A_MARK, MSIOF1_TXD_A_MARK, TS_SCK0_A_MARK, STP_ISCLK_0_A_MARK,
+	RIF0_D1_A_MARK, RIF2_D0_A_MARK, SSI_SCK4_MARK, HRX2_A_MARK,
+	MSIOF1_SCK_A_MARK, TS_SDAT0_A_MARK, STP_ISD_0_A_MARK, RIF0_CLK_A_MARK,
+	RIF2_CLK_A_MARK, SSI_WS4_MARK, HTX2_A_MARK, MSIOF1_SYNC_A_MARK,
+	TS_SDEN0_A_MARK, STP_ISEN_0_A_MARK, RIF0_SYNC_A_MARK, RIF2_SYNC_A_MARK,
+	SSI_SDATA4_MARK, HSCK2_A_MARK, MSIOF1_RXD_A_MARK, TS_SPSYNC0_A_MARK,
+	STP_ISSYNC_0_A_MARK, RIF0_D0_A_MARK, RIF2_D1_A_MARK,
+
+	/* IPSR15 */
+	SSI_SCK6_MARK, USB2_PWEN_MARK, SIM0_RST_D_MARK, SSI_WS6_MARK,
+	USB2_OVC_MARK, SIM0_D_D_MARK, SSI_SDATA6_MARK, SIM0_CLK_D_MARK,
+	SATA_DEVSLP_A_MARK, SSI_SCK78_MARK, HRX2_B_MARK, MSIOF1_SCK_C_MARK,
+	TS_SCK1_A_MARK, STP_ISCLK_1_A_MARK, RIF1_CLK_A_MARK, RIF3_CLK_A_MARK,
+	SSI_WS78_MARK, HTX2_B_MARK, MSIOF1_SYNC_C_MARK, TS_SDAT1_A_MARK,
+	STP_ISD_1_A_MARK, RIF1_SYNC_A_MARK, RIF3_SYNC_A_MARK, SSI_SDATA7_MARK,
+	HCTS2_N_B_MARK, MSIOF1_RXD_C_MARK, TS_SDEN1_A_MARK, STP_ISEN_1_A_MARK,
+	RIF1_D0_A_MARK, RIF3_D0_A_MARK, TCLK2_A_MARK, SSI_SDATA8_MARK,
+	HRTS2_N_B_MARK, MSIOF1_TXD_C_MARK, TS_SPSYNC1_A_MARK,
+	STP_ISSYNC_1_A_MARK, RIF1_D1_A_MARK, RIF3_D1_A_MARK, SSI_SDATA9_A_MARK,
+	HSCK2_B_MARK, MSIOF1_SS1_C_MARK, HSCK1_A_MARK, SSI_WS1_B_MARK,
+	SCK1_MARK, STP_IVCXO27_1_A_MARK, SCK5_MARK,
+
+	/* IPSR16 */
+	AUDIO_CLKA_A_MARK, CC5_OSCOUT_MARK, AUDIO_CLKB_B_MARK, SCIF_CLK_A_MARK,
+	STP_IVCXO27_1_D_MARK, REMOCON_A_MARK, TCLK1_A_MARK, USB0_PWEN_MARK,
+	SIM0_RST_C_MARK, TS_SCK1_D_MARK, STP_ISCLK_1_D_MARK, BPFCLK_B_MARK,
+	RIF3_CLK_B_MARK, USB0_OVC_MARK, SIM0_D_C_MARK, TS_SDAT1_D_MARK,
+	STP_ISD_1_D_MARK, RIF3_SYNC_B_MARK, USB1_PWEN_MARK, SIM0_CLK_C_MARK,
+	SSI_SCK1_A_MARK, TS_SCK0_E_MARK, STP_ISCLK_0_E_MARK, FMCLK_B_MARK,
+	RIF2_CLK_B_MARK, SPEEDIN_A_MARK, USB1_OVC_MARK, MSIOF1_SS2_C_MARK,
+	SSI_WS1_A_MARK, TS_SDAT0_E_MARK, STP_ISD_0_E_MARK, FMIN_B_MARK,
+	RIF2_SYNC_B_MARK, REMOCON_B_MARK, USB30_PWEN_MARK, AUDIO_CLKOUT_B_MARK,
+	SSI_SCK2_B_MARK, TS_SDEN1_D_MARK, STP_ISEN_1_D_MARK, STP_OPWM_0_E_MARK,
+	RIF3_D0_B_MARK, TCLK2_B_MARK, TPU0TO0_MARK, USB30_OVC_MARK,
+	AUDIO_CLKOUT1_B_MARK, SSI_WS2_B_MARK, TS_SPSYNC1_D_MARK,
+	STP_ISSYNC_1_D_MARK, STP_IVCXO27_0_E_MARK, RIF3_D1_B_MARK,
+	FSO_TOE_B_MARK, TPU0TO1_MARK,
+
+	/* IPSR17 */
+	USB31_PWEN_MARK, AUDIO_CLKOUT2_B_MARK, SSI_SCK9_B_MARK, TS_SDEN0_E_MARK,
+	STP_ISEN_0_E_MARK, RIF2_D0_B_MARK, TPU0TO2_MARK, USB31_OVC_MARK,
+	AUDIO_CLKOUT3_B_MARK, SSI_WS9_B_MARK, TS_SPSYNC0_E_MARK,
+	STP_ISSYNC_0_E_MARK, RIF2_D1_B_MARK, TPU0TO3_MARK,
+
+	/* MOD_SEL0 */
+	SEL_5LINE_0_MARK, SEL_5LINE_1_MARK, SEL_ADG_0_MARK, SEL_ADG_1_MARK,
+	SEL_ADG_2_MARK, SEL_ADG_3_MARK, SEL_CANFD0_0_MARK, SEL_CANFD0_1_MARK,
+	SEL_DRIF0_0_MARK, SEL_DRIF0_1_MARK, SEL_DRIF0_2_MARK, SEL_DRIF0_3_MARK,
+	SEL_DRIF1_0_MARK, SEL_DRIF1_1_MARK, SEL_DRIF1_2_MARK, SEL_DRIF1_3_MARK,
+	SEL_DRIF2_0_MARK, SEL_DRIF2_1_MARK, SEL_DRIF3_0_MARK, SEL_DRIF3_1_MARK,
+	SEL_ETHERAVB_0_MARK, SEL_ETHERAVB_1_MARK, SEL_FM_0_MARK, SEL_FM_1_MARK,
+	SEL_FSO_0_MARK, SEL_FSO_1_MARK, SEL_HSCIF1_0_MARK, SEL_HSCIF1_1_MARK,
+	SEL_HSCIF2_0_MARK, SEL_HSCIF2_1_MARK, SEL_HSCIF3_0_MARK,
+	SEL_HSCIF3_1_MARK, SEL_HSCIF3_2_MARK, SEL_HSCIF3_3_MARK,
+	SEL_HSCIF4_0_MARK, SEL_HSCIF4_1_MARK, SEL_I2C1_0_MARK, SEL_I2C1_1_MARK,
+	SEL_I2C2_0_MARK, SEL_I2C2_1_MARK, SEL_I2C6_0_MARK, SEL_I2C6_1_MARK,
+	SEL_I2C6_2_MARK, SEL_I2C6_3_MARK, SEL_IEBUS_0_MARK, SEL_IEBUS_1_MARK,
+	SEL_LBSC_0_MARK, SEL_LBSC_1_MARK, SEL_MSIOF1_0_MARK, SEL_MSIOF1_1_MARK,
+	SEL_MSIOF1_2_MARK, SEL_MSIOF1_3_MARK, SEL_MSIOF1_4_MARK,
+	SEL_MSIOF1_5_MARK, SEL_MSIOF1_6_MARK, SEL_MSIOF1_7_MARK,
+	SEL_MSIOF2_0_MARK, SEL_MSIOF2_1_MARK,SEL_MSIOF2_2_MARK,
+	SEL_MSIOF2_3_MARK, SEL_MSIOF3_0_MARK, SEL_MSIOF3_1_MARK,
+	SEL_MSIOF3_2_MARK, SEL_MSIOF3_3_MARK,
+
+	/* MOD_SEL1 */
+	SEL_PWM1_0_MARK, SEL_PWM1_1_MARK, SEL_PWM2_0_MARK, SEL_PWM2_1_MARK,
+	SEL_PWM3_0_MARK, SEL_PWM3_1_MARK, SEL_PWM4_0_MARK, SEL_PWM4_1_MARK,
+	SEL_PWM5_0_MARK, SEL_PWM5_1_MARK, SEL_PWM6_0_MARK, SEL_PWM6_1_MARK,
+	SEL_RCAN0_0_MARK, SEL_RCAN0_1_MARK, SEL_RDS_0_MARK, SEL_RDS_1_MARK,
+	SEL_RDS_2_MARK, SEL_RDS_3_MARK,	SEL_REMOCON_0_MARK, SEL_REMOCON_1_MARK,
+	SEL_SCIF_0_MARK, SEL_SCIF_1_MARK, SEL_SCIF1_0_MARK, SEL_SCIF1_1_MARK,
+	SEL_SCIF2_0_MARK, SEL_SCIF2_1_MARK, SEL_SCIF3_0_MARK, SEL_SCIF3_1_MARK,
+	SEL_SCIF4_0_MARK, SEL_SCIF4_1_MARK, SEL_SCIF4_2_MARK, SEL_SCIF4_3_MARK,
+	SEL_SDHI2_0_MARK, SEL_SDHI2_1_MARK, SEL_SIMCARD_0_MARK,
+	SEL_SIMCARD_1_MARK, SEL_SIMCARD_2_MARK, SEL_SIMCARD_3_MARK,
+	SEL_SPEED_PULSE_IF_0_MARK, SEL_SPEED_PULSE_IF_1_MARK,
+	SEL_SSI_0_MARK, SEL_SSI_1_MARK, SEL_SSP1_0_0_MARK, SEL_SSP1_0_1_MARK,
+	SEL_SSP1_0_2_MARK, SEL_SSP1_0_3_MARK, SEL_SSP1_0_4_MARK,
+	SEL_SSP1_0_5_MARK, SEL_SSP1_0_6_MARK, SEL_SSP1_0_7_MARK,
+	SEL_SSP1_1_0_MARK, SEL_SSP1_1_1_MARK, SEL_SSP1_1_2_MARK,
+	SEL_SSP1_1_3_MARK, SEL_TIMER_TMU_0_MARK, SEL_TIMER_TMU_1_MARK,
+	SEL_TSIF0_0_MARK, SEL_TSIF0_1_MARK, SEL_TSIF0_2_MARK, SEL_TSIF0_3_MARK,
+	SEL_TSIF0_4_MARK, SEL_TSIF0_5_MARK, SEL_TSIF0_6_MARK, SEL_TSIF0_7_MARK,
+	SEL_TSIF1_0_MARK, SEL_TSIF1_1_MARK, SEL_TSIF1_2_MARK, SEL_TSIF1_3_MARK,
+
+	/* MOD_SEL2 */
+	SEL_VIN4_0_MARK, SEL_VIN4_1_MARK, SEL_VSP_0_MARK, SEL_VSP_1_MARK,
+	SEL_VSP_2_MARK, SEL_VSP_3_MARK, I2C_SEL_0_0_MARK, I2C_SEL_0_1_MARK,
+	I2C_SEL_3_0_MARK, I2C_SEL_3_1_MARK, I2C_SEL_5_0_MARK, I2C_SEL_5_1_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static const u16 pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(),
+
+	/* IPSR0 */
+	PINMUX_IPSR_DATA(IP0_3_0, AVB_MDC),
+	PINMUX_IPSR_MODSEL_DATA(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
+
+	PINMUX_IPSR_DATA(IP0_7_4, AVB_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP0_7_4, SCK4_A, SEL_SCIF4_0),
+
+	PINMUX_IPSR_DATA(IP0_11_8, AVB_PHY_INT),
+	PINMUX_IPSR_MODSEL_DATA(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP0_11_8, RX4_A, SEL_SCIF4_0),
+
+	PINMUX_IPSR_DATA(IP0_15_12, AVB_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, TX4_A, SEL_SCIF4_0),
+
+	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
+	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
+
+	PINMUX_IPSR_MODSEL_DATA(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
+	PINMUX_IPSR_MODSEL_DATA(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
+
+	PINMUX_IPSR_DATA(IP0_27_24, IRQ0),
+	PINMUX_IPSR_DATA(IP0_27_24, QPOLB),
+	PINMUX_IPSR_DATA(IP0_27_24, DU_CDE),
+	PINMUX_IPSR_MODSEL_DATA(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
+
+	PINMUX_IPSR_DATA(IP0_31_28, IRQ1),
+	PINMUX_IPSR_DATA(IP0_31_28, QPOLA),
+	PINMUX_IPSR_DATA(IP0_31_28, DU_DISP),
+	PINMUX_IPSR_MODSEL_DATA(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
+
+	/* IPSR1 */
+	PINMUX_IPSR_DATA(IP1_3_0, IRQ2),
+	PINMUX_IPSR_DATA(IP1_3_0, QCPV_QDE),
+	PINMUX_IPSR_DATA(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
+	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, PWM3_B, SEL_PWM3_1),
+
+	PINMUX_IPSR_DATA(IP1_7_4, IRQ3),
+	PINMUX_IPSR_DATA(IP1_7_4, QSTVB_QVE),
+	PINMUX_IPSR_DATA(IP1_7_4, DU_DOTCLKOUT1),
+	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, PWM4_B, SEL_PWM4_1),
+
+	PINMUX_IPSR_DATA(IP1_11_8, IRQ4),
+	PINMUX_IPSR_DATA(IP1_11_8, QSTH_QHS),
+	PINMUX_IPSR_DATA(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
+	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, PWM5_B, SEL_PWM5_1),
+
+	PINMUX_IPSR_DATA(IP1_15_12, IRQ5),
+	PINMUX_IPSR_DATA(IP1_15_12, QSTB_QHE),
+	PINMUX_IPSR_DATA(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
+	PINMUX_IPSR_MODSEL_DATA(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP1_15_12, PWM6_B, SEL_PWM6_1),
+
+	PINMUX_IPSR_DATA(IP1_19_16, PWM0),
+	PINMUX_IPSR_DATA(IP1_19_16, AVB_AVTP_PPS),
+	PINMUX_IPSR_MODSEL_DATA(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP1_19_16, IECLK_B, SEL_IEBUS_1),
+
+	PINMUX_IPSR_DATA(IP1_31_28, A0),
+	PINMUX_IPSR_DATA(IP1_31_28, LCDOUT16),
+	PINMUX_IPSR_MODSEL_DATA(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
+	PINMUX_IPSR_DATA(IP1_31_28, VI4_DATA8),
+	PINMUX_IPSR_DATA(IP1_31_28, DU_DB0),
+	PINMUX_IPSR_MODSEL_DATA(IP1_31_28, PWM3_A, SEL_PWM3_0),
+
+	/* IPSR2 */
+	PINMUX_IPSR_DATA(IP2_3_0, A1),
+	PINMUX_IPSR_DATA(IP2_3_0, LCDOUT17),
+	PINMUX_IPSR_MODSEL_DATA(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
+	PINMUX_IPSR_DATA(IP2_3_0, VI4_DATA9),
+	PINMUX_IPSR_DATA(IP2_3_0, DU_DB1),
+	PINMUX_IPSR_MODSEL_DATA(IP2_3_0, PWM4_A, SEL_PWM4_0),
+
+	PINMUX_IPSR_DATA(IP2_7_4, A2),
+	PINMUX_IPSR_DATA(IP2_7_4, LCDOUT18),
+	PINMUX_IPSR_MODSEL_DATA(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
+	PINMUX_IPSR_DATA(IP2_7_4, VI4_DATA10),
+	PINMUX_IPSR_DATA(IP2_7_4, DU_DB2),
+	PINMUX_IPSR_MODSEL_DATA(IP2_7_4, PWM5_A, SEL_PWM5_0),
+
+	PINMUX_IPSR_DATA(IP2_11_8, A3),
+	PINMUX_IPSR_DATA(IP2_11_8, LCDOUT19),
+	PINMUX_IPSR_MODSEL_DATA(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
+	PINMUX_IPSR_DATA(IP2_11_8, VI4_DATA11),
+	PINMUX_IPSR_DATA(IP2_11_8, DU_DB3),
+	PINMUX_IPSR_MODSEL_DATA(IP2_11_8, PWM6_A, SEL_PWM6_0),
+
+	PINMUX_IPSR_DATA(IP2_15_12, A4),
+	PINMUX_IPSR_DATA(IP2_15_12, LCDOUT20),
+	PINMUX_IPSR_MODSEL_DATA(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
+	PINMUX_IPSR_DATA(IP2_15_12, VI4_DATA12),
+	PINMUX_IPSR_DATA(IP2_15_12, VI5_DATA12),
+	PINMUX_IPSR_DATA(IP2_15_12, DU_DB4),
+
+	PINMUX_IPSR_DATA(IP2_19_16, A5),
+	PINMUX_IPSR_DATA(IP2_19_16, LCDOUT21),
+	PINMUX_IPSR_MODSEL_DATA(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP2_19_16, SCK4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_DATA(IP2_19_16, VI4_DATA13),
+	PINMUX_IPSR_DATA(IP2_19_16, VI5_DATA13),
+	PINMUX_IPSR_DATA(IP2_19_16, DU_DB5),
+
+	PINMUX_IPSR_DATA(IP2_23_20, A6),
+	PINMUX_IPSR_DATA(IP2_23_20, LCDOUT22),
+	PINMUX_IPSR_MODSEL_DATA(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP2_23_20, RX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_DATA(IP2_23_20, VI4_DATA14),
+	PINMUX_IPSR_DATA(IP2_23_20, VI5_DATA14),
+	PINMUX_IPSR_DATA(IP2_23_20, DU_DB6),
+
+	PINMUX_IPSR_DATA(IP2_27_24, A7),
+	PINMUX_IPSR_DATA(IP2_27_24, LCDOUT23),
+	PINMUX_IPSR_MODSEL_DATA(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP2_27_24, TX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_DATA(IP2_27_24, VI4_DATA15),
+	PINMUX_IPSR_DATA(IP2_27_24, VI5_DATA15),
+	PINMUX_IPSR_DATA(IP2_27_24, DU_DB7),
+
+	PINMUX_IPSR_DATA(IP2_31_28, A8),
+	PINMUX_IPSR_MODSEL_DATA(IP2_31_28, RX3_B, SEL_SCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP2_31_28, SDA6_A, SEL_I2C6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
+	PINMUX_IPSR_MODSEL_DATA(IP2_31_28, PWM1_B, SEL_PWM1_1),
+
+	/* IPSR3 */
+	PINMUX_IPSR_DATA(IP3_3_0, A9),
+	PINMUX_IPSR_MODSEL_DATA(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
+	PINMUX_IPSR_DATA(IP3_3_0, VI5_VSYNC_N),
+
+	PINMUX_IPSR_DATA(IP3_7_4, A10),
+	PINMUX_IPSR_MODSEL_DATA(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
+	PINMUX_IPSR_DATA(IP3_7_4, VI5_HSYNC_N),
+
+	PINMUX_IPSR_DATA(IP3_11_8, A11),
+	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, TX3_B, SEL_SCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
+	PINMUX_IPSR_DATA(IP3_11_8, HSCK4),
+	PINMUX_IPSR_DATA(IP3_11_8, VI5_FIELD),
+	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCL6_A, SEL_I2C6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
+	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, PWM2_B, SEL_PWM2_1),
+
+	PINMUX_IPSR_DATA(IP3_15_12, A12),
+	PINMUX_IPSR_DATA(IP3_15_12, LCDOUT12),
+	PINMUX_IPSR_MODSEL_DATA(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
+	PINMUX_IPSR_MODSEL_DATA(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
+	PINMUX_IPSR_DATA(IP3_15_12, VI5_DATA8),
+	PINMUX_IPSR_DATA(IP3_15_12, DU_DG4),
+
+	PINMUX_IPSR_DATA(IP3_19_16, A13),
+	PINMUX_IPSR_DATA(IP3_19_16, LCDOUT13),
+	PINMUX_IPSR_MODSEL_DATA(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
+	PINMUX_IPSR_MODSEL_DATA(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
+	PINMUX_IPSR_DATA(IP3_19_16, VI5_DATA9),
+	PINMUX_IPSR_DATA(IP3_19_16, DU_DG5),
+
+	PINMUX_IPSR_DATA(IP3_23_20, A14),
+	PINMUX_IPSR_DATA(IP3_23_20, LCDOUT14),
+	PINMUX_IPSR_MODSEL_DATA(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
+	PINMUX_IPSR_DATA(IP3_23_20, HCTS4_N),
+	PINMUX_IPSR_DATA(IP3_23_20, VI5_DATA10),
+	PINMUX_IPSR_DATA(IP3_23_20, DU_DG6),
+
+	PINMUX_IPSR_DATA(IP3_27_24, A15),
+	PINMUX_IPSR_DATA(IP3_27_24, LCDOUT15),
+	PINMUX_IPSR_MODSEL_DATA(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
+	PINMUX_IPSR_DATA(IP3_27_24, HRTS4_N),
+	PINMUX_IPSR_DATA(IP3_27_24, VI5_DATA11),
+	PINMUX_IPSR_DATA(IP3_27_24, DU_DG7),
+
+	PINMUX_IPSR_DATA(IP3_31_28, A16),
+	PINMUX_IPSR_DATA(IP3_31_28, LCDOUT8),
+	PINMUX_IPSR_DATA(IP3_31_28, VI4_FIELD),
+	PINMUX_IPSR_DATA(IP3_31_28, DU_DG0),
+
+	/* IPSR4 */
+	PINMUX_IPSR_DATA(IP4_3_0, A17),
+	PINMUX_IPSR_DATA(IP4_3_0, LCDOUT9),
+	PINMUX_IPSR_DATA(IP4_3_0, VI4_VSYNC_N),
+	PINMUX_IPSR_DATA(IP4_3_0, DU_DG1),
+
+	PINMUX_IPSR_DATA(IP4_7_4, A18),
+	PINMUX_IPSR_DATA(IP4_7_4, LCDOUT10),
+	PINMUX_IPSR_DATA(IP4_7_4, VI4_HSYNC_N),
+	PINMUX_IPSR_DATA(IP4_7_4, DU_DG2),
+
+	PINMUX_IPSR_DATA(IP4_11_8, A19),
+	PINMUX_IPSR_DATA(IP4_11_8, LCDOUT11),
+	PINMUX_IPSR_DATA(IP4_11_8, VI4_CLKENB),
+	PINMUX_IPSR_DATA(IP4_11_8, DU_DG3),
+
+	PINMUX_IPSR_DATA(IP4_23_20, BS_N),
+	PINMUX_IPSR_DATA(IP4_23_20, QSTVA_QVS),
+	PINMUX_IPSR_MODSEL_DATA(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
+	PINMUX_IPSR_DATA(IP4_23_20, SCK3),
+	PINMUX_IPSR_DATA(IP4_23_20, HSCK3),
+	PINMUX_IPSR_DATA(IP4_23_20, CAN1_TX),
+	PINMUX_IPSR_DATA(IP4_23_20, CANFD1_TX),
+	PINMUX_IPSR_DATA(IP4_23_20, IETX_A),
+
+	PINMUX_IPSR_DATA(IP4_27_24, RD_N),
+	PINMUX_IPSR_MODSEL_DATA(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
+	PINMUX_IPSR_MODSEL_DATA(IP4_27_24, RX3_A, SEL_SCIF3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
+
+	PINMUX_IPSR_DATA(IP4_31_28, RD_WR_N),
+	PINMUX_IPSR_MODSEL_DATA(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
+	PINMUX_IPSR_MODSEL_DATA(IP4_31_28, TX3_A, SEL_SCIF3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
+
+	/* IPSR5 */
+	PINMUX_IPSR_DATA(IP5_3_0, WE0_N),
+	PINMUX_IPSR_MODSEL_DATA(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
+	PINMUX_IPSR_DATA(IP5_3_0, CTS3_N),
+	PINMUX_IPSR_DATA(IP5_3_0, HCTS3_N),
+	PINMUX_IPSR_MODSEL_DATA(IP5_3_0, SCL6_B, SEL_I2C6_1),
+	PINMUX_IPSR_DATA(IP5_3_0, CAN_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP5_3_0, IECLK_A, SEL_IEBUS_0),
+
+	PINMUX_IPSR_DATA(IP5_7_4, WE1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
+	PINMUX_IPSR_DATA(IP5_7_4, RTS3_N_TANS),
+	PINMUX_IPSR_MODSEL_DATA(IP5_7_4, SDA6_B, SEL_I2C6_1),
+	PINMUX_IPSR_DATA(IP5_7_4, CAN1_RX),
+	PINMUX_IPSR_DATA(IP5_7_4, CANFD1_RX),
+	PINMUX_IPSR_MODSEL_DATA(IP5_7_4, IERX_A, SEL_IEBUS_0),
+
+	PINMUX_IPSR_MODSEL_DATA(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
+	PINMUX_IPSR_DATA(IP5_11_8, QCLK),
+	PINMUX_IPSR_DATA(IP5_11_8, VI4_CLK),
+	PINMUX_IPSR_DATA(IP5_11_8, DU_DOTCLKOUT0),
+
+	PINMUX_IPSR_DATA(IP5_15_12, D0),
+	PINMUX_IPSR_MODSEL_DATA(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
+	PINMUX_IPSR_DATA(IP5_15_12, VI4_DATA16),
+	PINMUX_IPSR_DATA(IP5_15_12, VI5_DATA0),
+
+	PINMUX_IPSR_DATA(IP5_19_16, D1),
+	PINMUX_IPSR_MODSEL_DATA(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
+	PINMUX_IPSR_DATA(IP5_19_16, VI4_DATA17),
+	PINMUX_IPSR_DATA(IP5_19_16, VI5_DATA1),
+
+	PINMUX_IPSR_DATA(IP5_23_20, D2),
+	PINMUX_IPSR_MODSEL_DATA(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
+	PINMUX_IPSR_DATA(IP5_23_20, VI4_DATA18),
+	PINMUX_IPSR_DATA(IP5_23_20, VI5_DATA2),
+
+	PINMUX_IPSR_DATA(IP5_27_24, D3),
+	PINMUX_IPSR_MODSEL_DATA(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
+	PINMUX_IPSR_DATA(IP5_27_24, VI4_DATA19),
+	PINMUX_IPSR_DATA(IP5_27_24, VI5_DATA3),
+
+	PINMUX_IPSR_DATA(IP5_31_28, D4),
+	PINMUX_IPSR_MODSEL_DATA(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
+	PINMUX_IPSR_DATA(IP5_31_28, VI4_DATA20),
+	PINMUX_IPSR_DATA(IP5_31_28, VI5_DATA4),
+
+	/* IPSR6 */
+	PINMUX_IPSR_DATA(IP6_3_0, D5),
+	PINMUX_IPSR_MODSEL_DATA(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
+	PINMUX_IPSR_DATA(IP6_3_0, VI4_DATA21),
+	PINMUX_IPSR_DATA(IP6_3_0, VI5_DATA5),
+
+	PINMUX_IPSR_DATA(IP6_7_4, D6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
+	PINMUX_IPSR_DATA(IP6_7_4, VI4_DATA22),
+	PINMUX_IPSR_DATA(IP6_7_4, VI5_DATA6),
+
+	PINMUX_IPSR_DATA(IP6_11_8, D7),
+	PINMUX_IPSR_MODSEL_DATA(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
+	PINMUX_IPSR_DATA(IP6_11_8, VI4_DATA23),
+	PINMUX_IPSR_DATA(IP6_11_8, VI5_DATA7),
+
+	PINMUX_IPSR_DATA(IP6_15_12, D8),
+	PINMUX_IPSR_DATA(IP6_15_12, LCDOUT0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_15_12, SCK4_C, SEL_SCIF4_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
+	PINMUX_IPSR_DATA(IP6_15_12, DU_DR0),
+
+	PINMUX_IPSR_DATA(IP6_19_16, D9),
+	PINMUX_IPSR_DATA(IP6_19_16, LCDOUT1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
+	PINMUX_IPSR_DATA(IP6_19_16, DU_DR1),
+
+	PINMUX_IPSR_DATA(IP6_23_20, D10),
+	PINMUX_IPSR_DATA(IP6_23_20, LCDOUT2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
+	PINMUX_IPSR_DATA(IP6_23_20, DU_DR2),
+
+	PINMUX_IPSR_DATA(IP6_27_24, D11),
+	PINMUX_IPSR_DATA(IP6_27_24, LCDOUT3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
+	PINMUX_IPSR_DATA(IP6_27_24, DU_DR3),
+
+	PINMUX_IPSR_DATA(IP6_31_28, D12),
+	PINMUX_IPSR_DATA(IP6_31_28, LCDOUT4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_28, RX4_C, SEL_SCIF4_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
+	PINMUX_IPSR_DATA(IP6_31_28, DU_DR4),
+
+	/* IPSR7 */
+	PINMUX_IPSR_DATA(IP7_3_0, D13),
+	PINMUX_IPSR_DATA(IP7_3_0, LCDOUT5),
+	PINMUX_IPSR_MODSEL_DATA(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP7_3_0, TX4_C, SEL_SCIF4_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
+	PINMUX_IPSR_DATA(IP7_3_0, DU_DR5),
+
+	PINMUX_IPSR_DATA(IP7_7_4, D14),
+	PINMUX_IPSR_DATA(IP7_7_4, LCDOUT6),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
+	PINMUX_IPSR_DATA(IP7_7_4, DU_DR6),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_4, SCL6_C, SEL_I2C6_2),
+
+	PINMUX_IPSR_DATA(IP7_11_8, D15),
+	PINMUX_IPSR_DATA(IP7_11_8, LCDOUT7),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
+	PINMUX_IPSR_DATA(IP7_11_8, DU_DR7),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_8, SDA6_C, SEL_I2C6_2),
+
+	PINMUX_IPSR_DATA(IP7_19_16, SD0_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_1_1),
+
+	PINMUX_IPSR_DATA(IP7_23_20, SD0_CMD),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
+
+	PINMUX_IPSR_DATA(IP7_27_24, SD0_DAT0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
+
+	PINMUX_IPSR_DATA(IP7_31_28, SD0_DAT1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
+
+	/* IPSR8 */
+	PINMUX_IPSR_DATA(IP8_3_0, SD0_DAT2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
+	PINMUX_IPSR_MODSEL_DATA(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
+
+	PINMUX_IPSR_DATA(IP8_7_4, SD0_DAT3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
+	PINMUX_IPSR_MODSEL_DATA(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
+
+	PINMUX_IPSR_DATA(IP8_11_8, SD1_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
+
+	PINMUX_IPSR_DATA(IP8_15_12, SD1_CMD),
+	PINMUX_IPSR_MODSEL_DATA(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
+
+	PINMUX_IPSR_DATA(IP8_23_20, SD1_DAT1),
+	PINMUX_IPSR_DATA(IP8_23_20, SD2_DAT5_MMC0_DAT5),
+	PINMUX_IPSR_MODSEL_DATA(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
+
+	PINMUX_IPSR_DATA(IP8_27_24, SD1_DAT2),
+	PINMUX_IPSR_DATA(IP8_27_24, SD2_DAT6_MMC0_DAT6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
+
+	PINMUX_IPSR_DATA(IP8_31_28, SD1_DAT3),
+	PINMUX_IPSR_DATA(IP8_31_28, SD2_DAT7_MMC0_DAT7),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
+
+	/* IPSR9 */
+
+	/* IPSR10 */
+	PINMUX_IPSR_DATA(IP10_27_24, SCK0),
+	PINMUX_IPSR_MODSEL_DATA(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP10_27_24, SDA2_A, SEL_I2C2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
+
+	PINMUX_IPSR_DATA(IP10_31_28, RX0),
+	PINMUX_IPSR_MODSEL_DATA(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
+
+	/* IPSR11 */
+	PINMUX_IPSR_DATA(IP11_3_0, TX0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
+
+	PINMUX_IPSR_DATA(IP11_7_4, CTS0_N),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
+
+	PINMUX_IPSR_DATA(IP11_11_8, RTS0_N_TANS),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_8, SCL2_A, SEL_I2C2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
+
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_12, RX1_A, SEL_SCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
+
+	PINMUX_IPSR_MODSEL_DATA(IP11_19_16, TX1_A, SEL_SCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
+
+	PINMUX_IPSR_DATA(IP11_23_20, CTS1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, HCTS1_N_A, SEL_HSCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, MSIOF1_RXD_B, SEL_MSIOF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, TS_SDEN1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, STP_ISEN_1_C, SEL_SSP1_1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, RIF1_D0_B, SEL_DRIF1_1),
+	PINMUX_IPSR_DATA(IP11_27_24, ADIDATA),
+
+	PINMUX_IPSR_DATA(IP11_27_24, RTS1_N_TANS),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
+	PINMUX_IPSR_DATA(IP11_27_24, ADICHS0),
+
+	PINMUX_IPSR_DATA(IP11_31_28, SCK2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
+	PINMUX_IPSR_DATA(IP11_31_28, ADICLK),
+
+	/* IPSR12 */
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_0, TX2_A, SEL_SCIF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_0, SCL1_A, SEL_I2C1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_0, FMCLK_A, SEL_FM_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
+
+	PINMUX_IPSR_MODSEL_DATA(IP12_7_4, RX2_A, SEL_SCIF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_7_4, SDA1_A, SEL_I2C1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_7_4, FMIN_A, SEL_FM_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
+
+	PINMUX_IPSR_DATA(IP12_11_8, HSCK0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
+
+	PINMUX_IPSR_DATA(IP12_15_12, HRX0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
+
+	PINMUX_IPSR_DATA(IP12_19_16, HTX0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
+
+	PINMUX_IPSR_DATA(IP12_23_20, HCTS0_N),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_20, RX2_B, SEL_SCIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
+
+	PINMUX_IPSR_DATA(IP12_27_24, HRTS0_N),
+	PINMUX_IPSR_MODSEL_DATA(IP12_27_24, TX2_B, SEL_SCIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_27_24, BPFCLK_A, SEL_FM_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
+
+	/* IPSR13 */
+	PINMUX_IPSR_DATA(IP13_7_4, MSIOF0_SS2),
+	PINMUX_IPSR_DATA(IP13_7_4, TX5),
+	PINMUX_IPSR_MODSEL_DATA(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
+	PINMUX_IPSR_MODSEL_DATA(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
+	PINMUX_IPSR_MODSEL_DATA(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
+
+	PINMUX_IPSR_DATA(IP13_11_8, MLB_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
+	PINMUX_IPSR_MODSEL_DATA(IP13_11_8, SCL1_B, SEL_I2C1_1),
+
+	PINMUX_IPSR_DATA(IP13_15_12, MLB_SIG),
+	PINMUX_IPSR_MODSEL_DATA(IP13_15_12, RX1_B, SEL_SCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
+	PINMUX_IPSR_MODSEL_DATA(IP13_15_12, SDA1_B, SEL_I2C1_1),
+
+	PINMUX_IPSR_DATA(IP13_19_16, MLB_DAT),
+	PINMUX_IPSR_MODSEL_DATA(IP13_19_16, TX1_B, SEL_SCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
+
+	PINMUX_IPSR_DATA(IP13_23_20, SSI_SCK0129),
+	PINMUX_IPSR_MODSEL_DATA(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
+
+	PINMUX_IPSR_DATA(IP13_27_24, SSI_WS0129),
+	PINMUX_IPSR_MODSEL_DATA(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
+
+	PINMUX_IPSR_DATA(IP13_31_28, SSI_SDATA0),
+	PINMUX_IPSR_MODSEL_DATA(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
+
+	/* IPSR14 */
+	PINMUX_IPSR_DATA(IP14_11_8, SSI_SCK34),
+	PINMUX_IPSR_MODSEL_DATA(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_1_0),
+
+	PINMUX_IPSR_DATA(IP14_15_12, SSI_WS34),
+	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
+
+	PINMUX_IPSR_DATA(IP14_19_16, SSI_SDATA3),
+	PINMUX_IPSR_MODSEL_DATA(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
+
+	PINMUX_IPSR_DATA(IP14_23_20, SSI_SCK4),
+	PINMUX_IPSR_MODSEL_DATA(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
+
+	PINMUX_IPSR_DATA(IP14_27_24, SSI_WS4),
+	PINMUX_IPSR_MODSEL_DATA(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
+
+	PINMUX_IPSR_DATA(IP14_31_28, SSI_SDATA4),
+	PINMUX_IPSR_MODSEL_DATA(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
+
+	/* IPSR15 */
+	PINMUX_IPSR_DATA(IP15_3_0, SSI_SCK6),
+	PINMUX_IPSR_DATA(IP15_3_0, USB2_PWEN),
+	PINMUX_IPSR_MODSEL_DATA(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
+
+	PINMUX_IPSR_DATA(IP15_7_4, SSI_WS6),
+	PINMUX_IPSR_DATA(IP15_7_4, USB2_OVC),
+	PINMUX_IPSR_MODSEL_DATA(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
+
+	PINMUX_IPSR_DATA(IP15_15_12, SSI_SCK78),
+	PINMUX_IPSR_MODSEL_DATA(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
+
+	PINMUX_IPSR_DATA(IP15_19_16, SSI_WS78),
+	PINMUX_IPSR_MODSEL_DATA(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
+
+	PINMUX_IPSR_DATA(IP15_23_20, SSI_SDATA7),
+	PINMUX_IPSR_MODSEL_DATA(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
+
+	PINMUX_IPSR_DATA(IP15_27_24, SSI_SDATA8),
+	PINMUX_IPSR_MODSEL_DATA(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
+
+	PINMUX_IPSR_MODSEL_DATA(IP15_31_28, SSI_SDATA9_A, SEL_HSCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
+	PINMUX_IPSR_DATA(IP15_31_28, SCK1),
+	PINMUX_IPSR_MODSEL_DATA(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
+	PINMUX_IPSR_DATA(IP15_31_28, SCK5),
+
+	/* IPSR16 */
+	PINMUX_IPSR_DATA(IP16_19_16, USB1_PWEN),
+	PINMUX_IPSR_MODSEL_DATA(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
+	PINMUX_IPSR_MODSEL_DATA(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP16_19_16, FMCLK_B, SEL_FM_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
+
+	PINMUX_IPSR_DATA(IP16_23_20, USB1_OVC),
+	PINMUX_IPSR_MODSEL_DATA(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP16_23_20, FMIN_B, SEL_FM_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
+
+	PINMUX_IPSR_DATA(IP16_27_24, USB30_PWEN),
+	PINMUX_IPSR_MODSEL_DATA(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
+	PINMUX_IPSR_DATA(IP16_27_24, TPU0TO0),
+
+	PINMUX_IPSR_DATA(IP16_31_28, USB30_OVC),
+	PINMUX_IPSR_MODSEL_DATA(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
+	PINMUX_IPSR_DATA(IP16_31_28, TPU0TO1),
+
+	/* IPSR17 */
+	PINMUX_IPSR_DATA(IP17_3_0, USB31_PWEN),
+	PINMUX_IPSR_MODSEL_DATA(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
+	PINMUX_IPSR_MODSEL_DATA(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
+	PINMUX_IPSR_DATA(IP17_3_0, TPU0TO2),
+
+	PINMUX_IPSR_DATA(IP17_7_4, USB31_OVC),
+	PINMUX_IPSR_MODSEL_DATA(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
+	PINMUX_IPSR_MODSEL_DATA(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
+	PINMUX_IPSR_DATA(IP17_7_4, TPU0TO3),
+
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+	PINMUX_GPIO_GP_ALL(),
+};
+
+/* - AUDIO CLOCK ------------------------------------------------------------ */
+
+/* - EtherAVB --------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+	/* AVB_LINK */
+	RCAR_GP_PIN(2, 12),
+};
+static const unsigned int avb_link_mux[] = {
+	AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+	/* AVB_MAGIC_ */
+	RCAR_GP_PIN(2, 10),
+};
+static const unsigned int avb_magic_mux[] = {
+	AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+	/* AVB_PHY_INT */
+	RCAR_GP_PIN(2, 11),
+};
+static const unsigned int avb_phy_int_mux[] = {
+	AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdc_pins[] = {
+	/* AVB_MDC */
+	RCAR_GP_PIN(2, 9),
+};
+static const unsigned int avb_mdc_mux[] = {
+	AVB_MDC_MARK,
+};
+static const unsigned int avb_avtp_pps_pins[] = {
+	/* AVB_AVTP_PPS */
+	RCAR_GP_PIN(2, 6),
+};
+static const unsigned int avb_avtp_pps_mux[] = {
+	AVB_AVTP_PPS_MARK,
+};
+static const unsigned int avb_avtp_match_a_pins[] = {
+	/* AVB_AVTP_MATCH_A */
+	RCAR_GP_PIN(2, 14),
+};
+static const unsigned int avb_avtp_match_a_mux[] = {
+	AVB_AVTP_MATCH_A_MARK,
+};
+static const unsigned int avb_avtp_capture_a_pins[] = {
+	/* AVB_AVTP_CAPTURE_A */
+	RCAR_GP_PIN(2, 13),
+};
+static const unsigned int avb_avtp_capture_a_mux[] = {
+	AVB_AVTP_CAPTURE_A_MARK,
+};
+static const unsigned int avb_avtp_match_b_pins[] = {
+	/*  AVB_AVTP_MATCH_B */
+	RCAR_GP_PIN(1, 8),
+};
+static const unsigned int avb_avtp_match_b_mux[] = {
+	AVB_AVTP_MATCH_B_MARK,
+};
+static const unsigned int avb_avtp_capture_b_pins[] = {
+	/* AVB_AVTP_CAPTURE_B */
+	RCAR_GP_PIN(1, 11),
+};
+static const unsigned int avb_avtp_capture_b_mux[] = {
+	AVB_AVTP_CAPTURE_B_MARK,
+};
+/* - AVS -------------------------------------------------------------------- */
+
+/* - CANFD ------------------------------------------------------------------ */
+
+/* - CRP -------------------------------------------------------------------- */
+
+/* - DRIF ------------------------------------------------------------------- */
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb888_pins[] = {
+	/* R[7:0] */
+	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(3, 8),
+
+	/* G[7:0] */
+	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
+
+	/* B[7:0] */
+	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
+	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
+	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
+};
+static const unsigned int du_rgb888_mux[] = {
+	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
+	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
+	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
+};
+static const unsigned int du_clk_out_0_pins[] = {
+	/* CLKOUT */
+	RCAR_GP_PIN(1, 27),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+	DU_DOTCLKOUT0_MARK
+};
+static const unsigned int du_clk_out_1_pins[] = {
+	/* CLKOUT */
+	RCAR_GP_PIN(2, 3),
+};
+static const unsigned int du_clk_out_1_mux[] = {
+	DU_DOTCLKOUT1_MARK
+};
+static const unsigned int du_sync_pins[] = {
+	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int du_sync_mux[] = {
+	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
+};
+static const unsigned int du_oddf_pins[] = {
+	/* EXDISP/EXODDF/EXCDE */
+	RCAR_GP_PIN(2, 2),
+};
+static const unsigned int du_oddf_mux[] = {
+	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+	/* CDE */
+	RCAR_GP_PIN(2, 0),
+};
+static const unsigned int du_cde_mux[] = {
+	DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+	/* DISP */
+	RCAR_GP_PIN(2, 1),
+};
+static const unsigned int du_disp_mux[] = {
+	DU_DISP_MARK,
+};
+/* - FM --------------------------------------------------------------------- */
+
+/* - FSO--------------------------------------------------------------------- */
+
+/* - GYRO ADC --------------------------------------------------------------- */
+
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi0_cec_pins[] = {
+	/* HDMI0_CEC */
+	RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+	HDMI0_CEC_MARK,
+};
+static const unsigned int hdmi1_cec_pins[] = {
+	/* HDMI0_CEC */
+	RCAR_GP_PIN(7, 3),
+};
+static const unsigned int hdmi1_cec_mux[] = {
+	HDMI1_CEC_MARK,
+};
+/* - HSCIF ------------------------------------------------------------------ */
+
+/* - I2C -------------------------------------------------------------------- */
+
+/* - IEBUS ------------------------------------------------------------------ */
+
+/* - INTC ------------------------------------------------------------------- */
+
+/* - LBSC ------------------------------------------------------------------- */
+
+/* - MLB -------------------------------------------------------------------- */
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 17),
+};
+static const unsigned int msiof0_clk_mux[] = {
+	MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(5, 18),
+};
+static const unsigned int msiof0_sync_mux[] = {
+	MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(5, 19),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+	MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(5, 21),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+	MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(5, 20),
+};
+static const unsigned int msiof0_txd_mux[] = {
+	MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(5, 22),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+	MSIOF0_RXD_MARK,
+};
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(6, 8),
+};
+static const unsigned int msiof1_clk_a_mux[] = {
+	MSIOF1_SCK_A_MARK,
+};
+static const unsigned int msiof1_sync_a_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(6, 9),
+};
+static const unsigned int msiof1_sync_a_mux[] = {
+	MSIOF1_SYNC_A_MARK,
+};
+static const unsigned int msiof1_ss1_a_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(6, 5),
+};
+static const unsigned int msiof1_ss1_a_mux[] = {
+	MSIOF1_SS1_A_MARK,
+};
+static const unsigned int msiof1_ss2_a_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(6, 6),
+};
+static const unsigned int msiof1_ss2_a_mux[] = {
+	MSIOF1_SS2_A_MARK,
+};
+static const unsigned int msiof1_txd_a_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(6, 7),
+};
+static const unsigned int msiof1_txd_a_mux[] = {
+	MSIOF1_TXD_A_MARK,
+};
+static const unsigned int msiof1_rxd_a_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(6, 10),
+};
+static const unsigned int msiof1_rxd_a_mux[] = {
+	MSIOF1_RXD_A_MARK,
+};
+static const unsigned int msiof1_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 9),
+};
+static const unsigned int msiof1_clk_b_mux[] = {
+	MSIOF1_SCK_B_MARK,
+};
+static const unsigned int msiof1_sync_b_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(5, 3),
+};
+static const unsigned int msiof1_sync_b_mux[] = {
+	MSIOF1_SYNC_B_MARK,
+};
+static const unsigned int msiof1_ss1_b_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(5, 4),
+};
+static const unsigned int msiof1_ss1_b_mux[] = {
+	MSIOF1_SS1_B_MARK,
+};
+static const unsigned int msiof1_ss2_b_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(5, 0),
+};
+static const unsigned int msiof1_ss2_b_mux[] = {
+	MSIOF1_SS2_B_MARK,
+};
+static const unsigned int msiof1_txd_b_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(5, 8),
+};
+static const unsigned int msiof1_txd_b_mux[] = {
+	MSIOF1_TXD_B_MARK,
+};
+static const unsigned int msiof1_rxd_b_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(5, 7),
+};
+static const unsigned int msiof1_rxd_b_mux[] = {
+	MSIOF1_RXD_B_MARK,
+};
+static const unsigned int msiof1_clk_c_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(6, 17),
+};
+static const unsigned int msiof1_clk_c_mux[] = {
+	MSIOF1_SCK_C_MARK,
+};
+static const unsigned int msiof1_sync_c_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(6, 18),
+};
+static const unsigned int msiof1_sync_c_mux[] = {
+	MSIOF1_SYNC_C_MARK,
+};
+static const unsigned int msiof1_ss1_c_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(6, 21),
+};
+static const unsigned int msiof1_ss1_c_mux[] = {
+	MSIOF1_SS1_C_MARK,
+};
+static const unsigned int msiof1_ss2_c_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(6, 27),
+};
+static const unsigned int msiof1_ss2_c_mux[] = {
+	MSIOF1_SS2_C_MARK,
+};
+static const unsigned int msiof1_txd_c_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(6, 20),
+};
+static const unsigned int msiof1_txd_c_mux[] = {
+	MSIOF1_TXD_C_MARK,
+};
+static const unsigned int msiof1_rxd_c_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(6, 19),
+};
+static const unsigned int msiof1_rxd_c_mux[] = {
+	MSIOF1_RXD_C_MARK,
+};
+static const unsigned int msiof1_clk_d_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 12),
+};
+static const unsigned int msiof1_clk_d_mux[] = {
+	MSIOF1_SCK_D_MARK,
+};
+static const unsigned int msiof1_sync_d_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(5, 15),
+};
+static const unsigned int msiof1_sync_d_mux[] = {
+	MSIOF1_SYNC_D_MARK,
+};
+static const unsigned int msiof1_ss1_d_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(5, 16),
+};
+static const unsigned int msiof1_ss1_d_mux[] = {
+	MSIOF1_SS1_D_MARK,
+};
+static const unsigned int msiof1_ss2_d_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(5, 21),
+};
+static const unsigned int msiof1_ss2_d_mux[] = {
+	MSIOF1_SS2_D_MARK,
+};
+static const unsigned int msiof1_txd_d_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(5, 14),
+};
+static const unsigned int msiof1_txd_d_mux[] = {
+	MSIOF1_TXD_D_MARK,
+};
+static const unsigned int msiof1_rxd_d_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(5, 13),
+};
+static const unsigned int msiof1_rxd_d_mux[] = {
+	MSIOF1_RXD_D_MARK,
+};
+static const unsigned int msiof1_clk_e_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 0),
+};
+static const unsigned int msiof1_clk_e_mux[] = {
+	MSIOF1_SCK_E_MARK,
+};
+static const unsigned int msiof1_sync_e_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(3, 1),
+};
+static const unsigned int msiof1_sync_e_mux[] = {
+	MSIOF1_SYNC_E_MARK,
+};
+static const unsigned int msiof1_ss1_e_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(3, 4),
+};
+static const unsigned int msiof1_ss1_e_mux[] = {
+	MSIOF1_SS1_E_MARK,
+};
+static const unsigned int msiof1_ss2_e_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(3, 5),
+};
+static const unsigned int msiof1_ss2_e_mux[] = {
+	MSIOF1_SS2_E_MARK,
+};
+static const unsigned int msiof1_txd_e_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(3, 3),
+};
+static const unsigned int msiof1_txd_e_mux[] = {
+	MSIOF1_TXD_E_MARK,
+};
+static const unsigned int msiof1_rxd_e_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(3, 2),
+};
+static const unsigned int msiof1_rxd_e_mux[] = {
+	MSIOF1_RXD_E_MARK,
+};
+static const unsigned int msiof1_clk_f_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 23),
+};
+static const unsigned int msiof1_clk_f_mux[] = {
+	MSIOF1_SCK_F_MARK,
+};
+static const unsigned int msiof1_sync_f_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(5, 24),
+};
+static const unsigned int msiof1_sync_f_mux[] = {
+	MSIOF1_SYNC_F_MARK,
+};
+static const unsigned int msiof1_ss1_f_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(6, 1),
+};
+static const unsigned int msiof1_ss1_f_mux[] = {
+	MSIOF1_SS1_F_MARK,
+};
+static const unsigned int msiof1_ss2_f_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(6, 2),
+};
+static const unsigned int msiof1_ss2_f_mux[] = {
+	MSIOF1_SS2_F_MARK,
+};
+static const unsigned int msiof1_txd_f_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(6, 0),
+};
+static const unsigned int msiof1_txd_f_mux[] = {
+	MSIOF1_TXD_F_MARK,
+};
+static const unsigned int msiof1_rxd_f_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(5, 25),
+};
+static const unsigned int msiof1_rxd_f_mux[] = {
+	MSIOF1_RXD_F_MARK,
+};
+static const unsigned int msiof1_clk_g_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 6),
+};
+static const unsigned int msiof1_clk_g_mux[] = {
+	MSIOF1_SCK_G_MARK,
+};
+static const unsigned int msiof1_sync_g_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(3, 7),
+};
+static const unsigned int msiof1_sync_g_mux[] = {
+	MSIOF1_SYNC_G_MARK,
+};
+static const unsigned int msiof1_ss1_g_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(3, 10),
+};
+static const unsigned int msiof1_ss1_g_mux[] = {
+	MSIOF1_SS1_G_MARK,
+};
+static const unsigned int msiof1_ss2_g_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(3, 11),
+};
+static const unsigned int msiof1_ss2_g_mux[] = {
+	MSIOF1_SS2_G_MARK,
+};
+static const unsigned int msiof1_txd_g_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(3, 9),
+};
+static const unsigned int msiof1_txd_g_mux[] = {
+	MSIOF1_TXD_G_MARK,
+};
+static const unsigned int msiof1_rxd_g_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(3, 8),
+};
+static const unsigned int msiof1_rxd_g_mux[] = {
+	MSIOF1_RXD_G_MARK,
+};
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(1, 9),
+};
+static const unsigned int msiof2_clk_a_mux[] = {
+	MSIOF2_SCK_A_MARK,
+};
+static const unsigned int msiof2_sync_a_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(1, 8),
+};
+static const unsigned int msiof2_sync_a_mux[] = {
+	MSIOF2_SYNC_A_MARK,
+};
+static const unsigned int msiof2_ss1_a_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof2_ss1_a_mux[] = {
+	MSIOF2_SS1_A_MARK,
+};
+static const unsigned int msiof2_ss2_a_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof2_ss2_a_mux[] = {
+	MSIOF2_SS2_A_MARK,
+};
+static const unsigned int msiof2_txd_a_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(1, 11),
+};
+static const unsigned int msiof2_txd_a_mux[] = {
+	MSIOF2_TXD_A_MARK,
+};
+static const unsigned int msiof2_rxd_a_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(1, 10),
+};
+static const unsigned int msiof2_rxd_a_mux[] = {
+	MSIOF2_RXD_A_MARK,
+};
+static const unsigned int msiof2_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof2_clk_b_mux[] = {
+	MSIOF2_SCK_B_MARK,
+};
+static const unsigned int msiof2_sync_b_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof2_sync_b_mux[] = {
+	MSIOF2_SYNC_B_MARK,
+};
+static const unsigned int msiof2_ss1_b_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(0, 0),
+};
+static const unsigned int msiof2_ss1_b_mux[] = {
+	MSIOF2_SS1_B_MARK,
+};
+static const unsigned int msiof2_ss2_b_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof2_ss2_b_mux[] = {
+	MSIOF2_SS2_B_MARK,
+};
+static const unsigned int msiof2_txd_b_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof2_txd_b_mux[] = {
+	MSIOF2_TXD_B_MARK,
+};
+static const unsigned int msiof2_rxd_b_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof2_rxd_b_mux[] = {
+	MSIOF2_RXD_B_MARK,
+};
+static const unsigned int msiof2_clk_c_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 12),
+};
+static const unsigned int msiof2_clk_c_mux[] = {
+	MSIOF2_SCK_C_MARK,
+};
+static const unsigned int msiof2_sync_c_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(2, 11),
+};
+static const unsigned int msiof2_sync_c_mux[] = {
+	MSIOF2_SYNC_C_MARK,
+};
+static const unsigned int msiof2_ss1_c_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(2, 10),
+};
+static const unsigned int msiof2_ss1_c_mux[] = {
+	MSIOF2_SS1_C_MARK,
+};
+static const unsigned int msiof2_ss2_c_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(2, 9),
+};
+static const unsigned int msiof2_ss2_c_mux[] = {
+	MSIOF2_SS2_C_MARK,
+};
+static const unsigned int msiof2_txd_c_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(2, 14),
+};
+static const unsigned int msiof2_txd_c_mux[] = {
+	MSIOF2_TXD_C_MARK,
+};
+static const unsigned int msiof2_rxd_c_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(2, 13),
+};
+static const unsigned int msiof2_rxd_c_mux[] = {
+	MSIOF2_RXD_C_MARK,
+};
+static const unsigned int msiof2_clk_d_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 8),
+};
+static const unsigned int msiof2_clk_d_mux[] = {
+	MSIOF2_SCK_D_MARK,
+};
+static const unsigned int msiof2_sync_d_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(0, 9),
+};
+static const unsigned int msiof2_sync_d_mux[] = {
+	MSIOF2_SYNC_D_MARK,
+};
+static const unsigned int msiof2_ss1_d_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(0, 12),
+};
+static const unsigned int msiof2_ss1_d_mux[] = {
+	MSIOF2_SS1_D_MARK,
+};
+static const unsigned int msiof2_ss2_d_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(0, 13),
+};
+static const unsigned int msiof2_ss2_d_mux[] = {
+	MSIOF2_SS2_D_MARK,
+};
+static const unsigned int msiof2_txd_d_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(0, 11),
+};
+static const unsigned int msiof2_txd_d_mux[] = {
+	MSIOF2_TXD_D_MARK,
+};
+static const unsigned int msiof2_rxd_d_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(0, 10),
+};
+static const unsigned int msiof2_rxd_d_mux[] = {
+	MSIOF2_RXD_D_MARK,
+};
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 0),
+};
+static const unsigned int msiof3_clk_a_mux[] = {
+	MSIOF3_SCK_A_MARK,
+};
+static const unsigned int msiof3_sync_a_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_sync_a_mux[] = {
+	MSIOF3_SYNC_A_MARK,
+};
+static const unsigned int msiof3_ss1_a_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(0, 14),
+};
+static const unsigned int msiof3_ss1_a_mux[] = {
+	MSIOF3_SS1_A_MARK,
+};
+static const unsigned int msiof3_ss2_a_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(0, 15),
+};
+static const unsigned int msiof3_ss2_a_mux[] = {
+	MSIOF3_SS2_A_MARK,
+};
+static const unsigned int msiof3_txd_a_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(1, 15),
+};
+static const unsigned int msiof3_txd_a_mux[] = {
+	MSIOF3_TXD_A_MARK,
+};
+static const unsigned int msiof3_rxd_a_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(1, 14),
+};
+static const unsigned int msiof3_rxd_a_mux[] = {
+	MSIOF3_RXD_A_MARK,
+};
+static const unsigned int msiof3_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof3_clk_b_mux[] = {
+	MSIOF3_SCK_B_MARK,
+};
+static const unsigned int msiof3_sync_b_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(1, 0),
+};
+static const unsigned int msiof3_sync_b_mux[] = {
+	MSIOF3_SYNC_B_MARK,
+};
+static const unsigned int msiof3_ss1_b_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(1, 4),
+};
+static const unsigned int msiof3_ss1_b_mux[] = {
+	MSIOF3_SS1_B_MARK,
+};
+static const unsigned int msiof3_ss2_b_pins[] = {
+	/* SS2 */
+	RCAR_GP_PIN(1, 5),
+};
+static const unsigned int msiof3_ss2_b_mux[] = {
+	MSIOF3_SS2_B_MARK,
+};
+static const unsigned int msiof3_txd_b_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(1, 1),
+};
+static const unsigned int msiof3_txd_b_mux[] = {
+	MSIOF3_TXD_B_MARK,
+};
+static const unsigned int msiof3_rxd_b_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof3_rxd_b_mux[] = {
+	MSIOF3_RXD_B_MARK,
+};
+static const unsigned int msiof3_clk_c_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(1, 12),
+};
+static const unsigned int msiof3_clk_c_mux[] = {
+	MSIOF3_SCK_C_MARK,
+};
+static const unsigned int msiof3_sync_c_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(1, 13),
+};
+static const unsigned int msiof3_sync_c_mux[] = {
+	MSIOF3_SYNC_C_MARK,
+};
+static const unsigned int msiof3_txd_c_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(1, 15),
+};
+static const unsigned int msiof3_txd_c_mux[] = {
+	MSIOF3_TXD_C_MARK,
+};
+static const unsigned int msiof3_rxd_c_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(1, 14),
+};
+static const unsigned int msiof3_rxd_c_mux[] = {
+	MSIOF3_RXD_C_MARK,
+};
+static const unsigned int msiof3_clk_d_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(1, 22),
+};
+static const unsigned int msiof3_clk_d_mux[] = {
+	MSIOF3_SCK_D_MARK,
+};
+static const unsigned int msiof3_sync_d_pins[] = {
+	/* SYNC */
+	RCAR_GP_PIN(1, 23),
+};
+static const unsigned int msiof3_sync_d_mux[] = {
+	MSIOF3_SYNC_D_MARK,
+};
+static const unsigned int msiof3_ss1_d_pins[] = {
+	/* SS1 */
+	RCAR_GP_PIN(1, 26),
+};
+static const unsigned int msiof3_ss1_d_mux[] = {
+	MSIOF3_SS1_D_MARK,
+};
+static const unsigned int msiof3_txd_d_pins[] = {
+	/* TXD */
+	RCAR_GP_PIN(1, 25),
+};
+static const unsigned int msiof3_txd_d_mux[] = {
+	MSIOF3_TXD_D_MARK,
+};
+static const unsigned int msiof3_rxd_d_pins[] = {
+	/* RXD */
+	RCAR_GP_PIN(1, 24),
+};
+static const unsigned int msiof3_rxd_d_mux[] = {
+	MSIOF3_RXD_D_MARK,
+};
+/* - PWM -------------------------------------------------------------------- */
+
+/* - RCAN ------------------------------------------------------------------- */
+
+/* - REMOCON ---------------------------------------------------------------- */
+
+/* - SATA ------------------------------------------------------------------- */
+
+/* - SATA ------------------------------------------------------------------- */
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif0_data_mux[] = {
+	RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 9),
+};
+static const unsigned int scif0_clk_b_mux[] = {
+	SCIF_CLK_B_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scif1_data_a_mux[] = {
+	RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(6, 21),
+};
+static const unsigned int scif1_clk_mux[] = {
+	SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+	RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+
+static const unsigned int scif1_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+};
+static const unsigned int scif1_data_b_mux[] = {
+	RX1_B_MARK, TX1_B_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int scif2_data_mux[] = {
+	RX2_A_MARK, TX2_A_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 9),
+};
+static const unsigned int scif2_clk_mux[] = {
+	SCK2_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int scif3_data_a_mux[] = {
+	RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scif3_clk_mux[] = {
+	SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+	RTS3_N_TANS_MARK, CTS3_N_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+};
+static const unsigned int scif3_data_b_mux[] = {
+	RX3_B_MARK, TX3_B_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scif4_data_a_mux[] = {
+	RX4_A_MARK, TX4_A_MARK,
+};
+static const unsigned int scif4_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif4_clk_a_mux[] = {
+	SCK4_A_MARK,
+};
+static const unsigned int scif4_ctrl_a_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scif4_ctrl_a_mux[] = {
+	RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int scif4_data_b_mux[] = {
+	RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif4_clk_b_mux[] = {
+	SCK4_B_MARK,
+};
+static const unsigned int scif4_ctrl_b_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int scif4_ctrl_b_mux[] = {
+	RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+};
+static const unsigned int scif4_data_c_mux[] = {
+	RX4_C_MARK, TX4_C_MARK,
+};
+static const unsigned int scif4_clk_c_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scif4_clk_c_mux[] = {
+	SCK4_C_MARK,
+};
+static const unsigned int scif4_ctrl_c_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif4_ctrl_c_mux[] = {
+	RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 21),
+};
+static const unsigned int scif5_data_mux[] = {
+	RX5_MARK, TX5_MARK,
+};
+static const unsigned int scif5_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(6, 21),
+};
+static const unsigned int scif5_clk_mux[] = {
+	SCK5_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+	SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+	SD0_DAT0_MARK, SD0_DAT1_MARK,
+	SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+	SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 12),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+	SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 13),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+	SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 8),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+	SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+	SD1_DAT0_MARK, SD1_DAT1_MARK,
+	SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+	SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+	SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+	SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(4, 2),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+	SD2_DAT0_MMC0_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+	SD2_DAT0_MMC0_DAT0_MARK, SD2_DAT1_MMC0_DAT1_MARK,
+	SD2_DAT2_MMC0_DAT2_MARK, SD2_DAT3_MMC0_DAT3_MARK,
+};
+static const unsigned int sdhi2_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
+	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
+	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int sdhi2_data8_mux[] = {
+	SD2_DAT0_MMC0_DAT0_MARK, SD2_DAT1_MMC0_DAT1_MARK,
+	SD2_DAT2_MMC0_DAT2_MARK, SD2_DAT3_MMC0_DAT3_MARK,
+	SD2_DAT4_MMC0_DAT4_MARK, SD2_DAT5_MMC0_DAT5_MARK,
+	SD2_DAT6_MMC0_DAT6_MARK, SD2_DAT7_MMC0_DAT7_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+	SD2_CLK_MMC0_CLK_MARK, SD2_CMD_MMC0_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_a_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(4, 13),
+};
+static const unsigned int sdhi2_cd_a_mux[] = {
+	SD2_CD_A_MARK,
+};
+static const unsigned int sdhi2_cd_b_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(5, 10),
+};
+static const unsigned int sdhi2_cd_b_mux[] = {
+	SD2_CD_B_MARK,
+};
+static const unsigned int sdhi2_wp_a_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(4, 14),
+};
+static const unsigned int sdhi2_wp_a_mux[] = {
+	SD2_WP_A_MARK,
+};
+static const unsigned int sdhi2_wp_b_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(5, 11),
+};
+static const unsigned int sdhi2_wp_b_mux[] = {
+	SD2_WP_B_MARK,
+};
+static const unsigned int sdhi2_ds_pins[] = {
+	/* DS */
+	RCAR_GP_PIN(4, 6),
+};
+static const unsigned int sdhi2_ds_mux[] = {
+	SD2_DS_MMC0_DS_MARK,
+};
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(4, 9),
+};
+static const unsigned int sdhi3_data1_mux[] = {
+	SD3_DAT0_MMC1_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
+	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+static const unsigned int sdhi3_data4_mux[] = {
+	SD3_DAT0_MMC1_DAT0_MARK, SD3_DAT1_MMC1_DAT1_MARK,
+	SD3_DAT2_MMC1_DAT2_MARK, SD3_DAT3_MMC1_DAT3_MARK,
+};
+static const unsigned int sdhi3_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
+	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int sdhi3_data8_mux[] = {
+	SD3_DAT0_MMC1_DAT0_MARK, SD3_DAT1_MMC1_DAT1_MARK,
+	SD3_DAT2_MMC1_DAT2_MARK, SD3_DAT3_MMC1_DAT3_MARK,
+	SD3_DAT4_MMC1_DAT4_MARK, SD3_DAT5_MMC1_DAT5_MARK,
+	SD3_DAT6_MMC1_DAT6_MARK, SD3_DAT7_MMC1_DAT7_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+	SD3_CLK_MMC1_CLK_MARK, SD3_CMD_MMC1_CMD_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(4, 15),
+};
+static const unsigned int sdhi3_cd_mux[] = {
+	SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(4, 16),
+};
+static const unsigned int sdhi3_wp_mux[] = {
+	SD3_WP_MARK,
+};
+static const unsigned int sdhi3_ds_pins[] = {
+	/* DS */
+	RCAR_GP_PIN(4, 17),
+};
+static const unsigned int sdhi3_ds_mux[] = {
+	SD3_DS_MMC1_DS_MARK,
+};
+/* - SIMcard ---------------------------------------------------------------- */
+
+/* - SPEED Pulse IF --------------------------------------------------------- */
+
+/* - SSI -------------------------------------------------------------------- */
+
+/* - SSP -------------------------------------------------------------------- */
+
+/* - TCON ------------------------------------------------------------------- */
+
+/* - TIMER TMU--------------------------------------------------------------- */
+
+/* - TPU -------------------------------------------------------------------- */
+
+/* - TSIF ------------------------------------------------------------------- */
+
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+	/* PWEN, OVC */
+	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int usb0_mux[] = {
+	USB0_PWEN_MARK, USB0_OVC_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+	/* PWEN, OVC */
+	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+static const unsigned int usb1_mux[] = {
+	USB1_PWEN_MARK, USB1_OVC_MARK,
+};
+/* - USB2 ------------------------------------------------------------------- */
+static const unsigned int usb2_pins[] = {
+	/* PWEN, OVC */
+	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
+};
+static const unsigned int usb2_mux[] = {
+	USB2_PWEN_MARK, USB2_OVC_MARK,
+};
+/* - USB30 ------------------------------------------------------------------- */
+static const unsigned int usb30_pins[] = {
+	/* PWEN, OVC */
+	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+};
+static const unsigned int usb30_mux[] = {
+	USB30_PWEN_MARK, USB30_OVC_MARK,
+};
+/* - USB31 ------------------------------------------------------------------- */
+static const unsigned int usb31_pins[] = {
+	/* PWEN, OVC */
+	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
+};
+static const unsigned int usb31_mux[] = {
+	USB31_PWEN_MARK, USB31_OVC_MARK,
+};
+/* - VIN -------------------------------------------------------------------- */
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(avb_link),
+	SH_PFC_PIN_GROUP(avb_magic),
+	SH_PFC_PIN_GROUP(avb_phy_int),
+	SH_PFC_PIN_GROUP(avb_mdc),
+	SH_PFC_PIN_GROUP(avb_avtp_pps),
+	SH_PFC_PIN_GROUP(avb_avtp_match_a),
+	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+	SH_PFC_PIN_GROUP(avb_avtp_match_b),
+	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+	SH_PFC_PIN_GROUP(du_rgb888),
+	SH_PFC_PIN_GROUP(du_clk_out_0),
+	SH_PFC_PIN_GROUP(du_clk_out_1),
+	SH_PFC_PIN_GROUP(du_sync),
+	SH_PFC_PIN_GROUP(du_oddf),
+	SH_PFC_PIN_GROUP(du_cde),
+	SH_PFC_PIN_GROUP(du_disp),
+	SH_PFC_PIN_GROUP(hdmi0_cec),
+	SH_PFC_PIN_GROUP(hdmi1_cec),
+	SH_PFC_PIN_GROUP(msiof0_clk),
+	SH_PFC_PIN_GROUP(msiof0_sync),
+	SH_PFC_PIN_GROUP(msiof0_ss1),
+	SH_PFC_PIN_GROUP(msiof0_ss2),
+	SH_PFC_PIN_GROUP(msiof0_txd),
+	SH_PFC_PIN_GROUP(msiof0_rxd),
+	SH_PFC_PIN_GROUP(msiof1_clk_a),
+	SH_PFC_PIN_GROUP(msiof1_sync_a),
+	SH_PFC_PIN_GROUP(msiof1_ss1_a),
+	SH_PFC_PIN_GROUP(msiof1_ss2_a),
+	SH_PFC_PIN_GROUP(msiof1_txd_a),
+	SH_PFC_PIN_GROUP(msiof1_rxd_a),
+	SH_PFC_PIN_GROUP(msiof1_clk_b),
+	SH_PFC_PIN_GROUP(msiof1_sync_b),
+	SH_PFC_PIN_GROUP(msiof1_ss1_b),
+	SH_PFC_PIN_GROUP(msiof1_ss2_b),
+	SH_PFC_PIN_GROUP(msiof1_txd_b),
+	SH_PFC_PIN_GROUP(msiof1_rxd_b),
+	SH_PFC_PIN_GROUP(msiof1_clk_c),
+	SH_PFC_PIN_GROUP(msiof1_sync_c),
+	SH_PFC_PIN_GROUP(msiof1_ss1_c),
+	SH_PFC_PIN_GROUP(msiof1_ss2_c),
+	SH_PFC_PIN_GROUP(msiof1_txd_c),
+	SH_PFC_PIN_GROUP(msiof1_rxd_c),
+	SH_PFC_PIN_GROUP(msiof1_clk_d),
+	SH_PFC_PIN_GROUP(msiof1_sync_d),
+	SH_PFC_PIN_GROUP(msiof1_ss1_d),
+	SH_PFC_PIN_GROUP(msiof1_ss2_d),
+	SH_PFC_PIN_GROUP(msiof1_txd_d),
+	SH_PFC_PIN_GROUP(msiof1_rxd_d),
+	SH_PFC_PIN_GROUP(msiof1_clk_e),
+	SH_PFC_PIN_GROUP(msiof1_sync_e),
+	SH_PFC_PIN_GROUP(msiof1_ss1_e),
+	SH_PFC_PIN_GROUP(msiof1_ss2_e),
+	SH_PFC_PIN_GROUP(msiof1_txd_e),
+	SH_PFC_PIN_GROUP(msiof1_rxd_e),
+	SH_PFC_PIN_GROUP(msiof1_clk_f),
+	SH_PFC_PIN_GROUP(msiof1_sync_f),
+	SH_PFC_PIN_GROUP(msiof1_ss1_f),
+	SH_PFC_PIN_GROUP(msiof1_ss2_f),
+	SH_PFC_PIN_GROUP(msiof1_txd_f),
+	SH_PFC_PIN_GROUP(msiof1_rxd_f),
+	SH_PFC_PIN_GROUP(msiof1_clk_g),
+	SH_PFC_PIN_GROUP(msiof1_sync_g),
+	SH_PFC_PIN_GROUP(msiof1_ss1_g),
+	SH_PFC_PIN_GROUP(msiof1_ss2_g),
+	SH_PFC_PIN_GROUP(msiof1_txd_g),
+	SH_PFC_PIN_GROUP(msiof1_rxd_g),
+	SH_PFC_PIN_GROUP(msiof2_clk_a),
+	SH_PFC_PIN_GROUP(msiof2_sync_a),
+	SH_PFC_PIN_GROUP(msiof2_ss1_a),
+	SH_PFC_PIN_GROUP(msiof2_ss2_a),
+	SH_PFC_PIN_GROUP(msiof2_txd_a),
+	SH_PFC_PIN_GROUP(msiof2_rxd_a),
+	SH_PFC_PIN_GROUP(msiof2_clk_b),
+	SH_PFC_PIN_GROUP(msiof2_sync_b),
+	SH_PFC_PIN_GROUP(msiof2_ss1_b),
+	SH_PFC_PIN_GROUP(msiof2_ss2_b),
+	SH_PFC_PIN_GROUP(msiof2_txd_b),
+	SH_PFC_PIN_GROUP(msiof2_rxd_b),
+	SH_PFC_PIN_GROUP(msiof2_clk_c),
+	SH_PFC_PIN_GROUP(msiof2_sync_c),
+	SH_PFC_PIN_GROUP(msiof2_ss1_c),
+	SH_PFC_PIN_GROUP(msiof2_ss2_c),
+	SH_PFC_PIN_GROUP(msiof2_txd_c),
+	SH_PFC_PIN_GROUP(msiof2_rxd_c),
+	SH_PFC_PIN_GROUP(msiof2_clk_d),
+	SH_PFC_PIN_GROUP(msiof2_sync_d),
+	SH_PFC_PIN_GROUP(msiof2_ss1_d),
+	SH_PFC_PIN_GROUP(msiof2_ss2_d),
+	SH_PFC_PIN_GROUP(msiof2_txd_d),
+	SH_PFC_PIN_GROUP(msiof2_rxd_d),
+	SH_PFC_PIN_GROUP(msiof3_clk_a),
+	SH_PFC_PIN_GROUP(msiof3_sync_a),
+	SH_PFC_PIN_GROUP(msiof3_ss1_a),
+	SH_PFC_PIN_GROUP(msiof3_ss2_a),
+	SH_PFC_PIN_GROUP(msiof3_txd_a),
+	SH_PFC_PIN_GROUP(msiof3_rxd_a),
+	SH_PFC_PIN_GROUP(msiof3_clk_b),
+	SH_PFC_PIN_GROUP(msiof3_sync_b),
+	SH_PFC_PIN_GROUP(msiof3_ss1_b),
+	SH_PFC_PIN_GROUP(msiof3_ss2_b),
+	SH_PFC_PIN_GROUP(msiof3_txd_b),
+	SH_PFC_PIN_GROUP(msiof3_rxd_b),
+	SH_PFC_PIN_GROUP(msiof3_clk_c),
+	SH_PFC_PIN_GROUP(msiof3_sync_c),
+	SH_PFC_PIN_GROUP(msiof3_txd_c),
+	SH_PFC_PIN_GROUP(msiof3_rxd_c),
+	SH_PFC_PIN_GROUP(msiof3_clk_d),
+	SH_PFC_PIN_GROUP(msiof3_sync_d),
+	SH_PFC_PIN_GROUP(msiof3_ss1_d),
+	SH_PFC_PIN_GROUP(msiof3_txd_d),
+	SH_PFC_PIN_GROUP(msiof3_rxd_d),
+	SH_PFC_PIN_GROUP(scif0_data),
+	SH_PFC_PIN_GROUP(scif0_clk_b),
+	SH_PFC_PIN_GROUP(scif1_data_a),
+	SH_PFC_PIN_GROUP(scif1_clk),
+	SH_PFC_PIN_GROUP(scif1_ctrl),
+	SH_PFC_PIN_GROUP(scif1_data_b),
+	SH_PFC_PIN_GROUP(scif2_data),
+	SH_PFC_PIN_GROUP(scif2_clk),
+	SH_PFC_PIN_GROUP(scif3_data_a),
+	SH_PFC_PIN_GROUP(scif3_clk),
+	SH_PFC_PIN_GROUP(scif3_ctrl),
+	SH_PFC_PIN_GROUP(scif3_data_b),
+	SH_PFC_PIN_GROUP(scif4_data_a),
+	SH_PFC_PIN_GROUP(scif4_clk_a),
+	SH_PFC_PIN_GROUP(scif4_ctrl_a),
+	SH_PFC_PIN_GROUP(scif4_data_b),
+	SH_PFC_PIN_GROUP(scif4_clk_b),
+	SH_PFC_PIN_GROUP(scif4_ctrl_b),
+	SH_PFC_PIN_GROUP(scif4_data_c),
+	SH_PFC_PIN_GROUP(scif4_clk_c),
+	SH_PFC_PIN_GROUP(scif4_ctrl_c),
+	SH_PFC_PIN_GROUP(scif5_data),
+	SH_PFC_PIN_GROUP(scif5_clk),
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_data1),
+	SH_PFC_PIN_GROUP(sdhi1_data4),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_cd),
+	SH_PFC_PIN_GROUP(sdhi1_wp),
+	SH_PFC_PIN_GROUP(sdhi2_data1),
+	SH_PFC_PIN_GROUP(sdhi2_data4),
+	SH_PFC_PIN_GROUP(sdhi2_data8),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_cd_a),
+	SH_PFC_PIN_GROUP(sdhi2_wp_a),
+	SH_PFC_PIN_GROUP(sdhi2_cd_b),
+	SH_PFC_PIN_GROUP(sdhi2_wp_b),
+	SH_PFC_PIN_GROUP(sdhi2_ds),
+	SH_PFC_PIN_GROUP(sdhi3_data1),
+	SH_PFC_PIN_GROUP(sdhi3_data4),
+	SH_PFC_PIN_GROUP(sdhi3_data8),
+	SH_PFC_PIN_GROUP(sdhi3_ctrl),
+	SH_PFC_PIN_GROUP(sdhi3_cd),
+	SH_PFC_PIN_GROUP(sdhi3_wp),
+	SH_PFC_PIN_GROUP(sdhi3_ds),
+	SH_PFC_PIN_GROUP(usb0),
+	SH_PFC_PIN_GROUP(usb1),
+	SH_PFC_PIN_GROUP(usb2),
+	SH_PFC_PIN_GROUP(usb30),
+	SH_PFC_PIN_GROUP(usb31),
+};
+
+static const char * const avb_groups[] = {
+	"avb_link",
+	"avb_magic",
+	"avb_phy_int",
+	"avb_mdc",
+	"avb_avtp_pps",
+	"avb_avtp_match_a",
+	"avb_avtp_capture_a",
+	"avb_avtp_match_b",
+	"avb_avtp_capture_b",
+};
+
+static const char * const du_groups[] = {
+	"du_rgb888",
+	"du_clk_out_0",
+	"du_clk_out_1",
+	"du_sync",
+	"du_oddf",
+	"du_cde",
+	"du_disp",
+};
+
+static const char * const hdmi0_groups[] = {
+	"hdmi0_cec",
+};
+
+static const char * const hdmi1_groups[] = {
+	"hdmi1_cec",
+};
+
+static const char * const msiof0_groups[] = {
+	"msiof0_clk",
+	"msiof0_sync",
+	"msiof0_ss1",
+	"msiof0_ss2",
+	"msiof0_txd",
+	"msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+	"msiof1_clk_a",
+	"msiof1_sync_a",
+	"msiof1_ss1_a",
+	"msiof1_ss2_a",
+	"msiof1_txd_a",
+	"msiof1_rxd_a",
+	"msiof1_clk_b",
+	"msiof1_sync_b",
+	"msiof1_ss1_b",
+	"msiof1_ss2_b",
+	"msiof1_txd_b",
+	"msiof1_rxd_b",
+	"msiof1_clk_c",
+	"msiof1_sync_c",
+	"msiof1_ss1_c",
+	"msiof1_ss2_c",
+	"msiof1_txd_c",
+	"msiof1_rxd_c",
+	"msiof1_clk_d",
+	"msiof1_sync_d",
+	"msiof1_ss1_d",
+	"msiof1_ss2_d",
+	"msiof1_txd_d",
+	"msiof1_rxd_d",
+	"msiof1_clk_e",
+	"msiof1_sync_e",
+	"msiof1_ss1_e",
+	"msiof1_ss2_e",
+	"msiof1_txd_e",
+	"msiof1_rxd_e",
+	"msiof1_clk_f",
+	"msiof1_sync_f",
+	"msiof1_ss1_f",
+	"msiof1_ss2_f",
+	"msiof1_txd_f",
+	"msiof1_rxd_f",
+	"msiof1_clk_g",
+	"msiof1_sync_g",
+	"msiof1_ss1_g",
+	"msiof1_ss2_g",
+	"msiof1_txd_g",
+	"msiof1_rxd_g",
+};
+
+static const char * const msiof2_groups[] = {
+	"msiof2_clk_a",
+	"msiof2_sync_a",
+	"msiof2_ss1_a",
+	"msiof2_ss2_a",
+	"msiof2_txd_a",
+	"msiof2_rxd_a",
+	"msiof2_clk_b",
+	"msiof2_sync_b",
+	"msiof2_ss1_b",
+	"msiof2_ss2_b",
+	"msiof2_txd_b",
+	"msiof2_rxd_b",
+	"msiof2_clk_c",
+	"msiof2_sync_c",
+	"msiof2_ss1_c",
+	"msiof2_ss2_c",
+	"msiof2_txd_c",
+	"msiof2_rxd_c",
+	"msiof2_clk_d",
+	"msiof2_sync_d",
+	"msiof2_ss1_d",
+	"msiof2_ss2_d",
+	"msiof2_txd_d",
+	"msiof2_rxd_d",
+};
+
+static const char * const msiof3_groups[] = {
+	"msiof3_clk_a",
+	"msiof3_sync_a",
+	"msiof3_ss1_a",
+	"msiof3_ss2_a",
+	"msiof3_txd_a",
+	"msiof3_rxd_a",
+	"msiof3_clk_b",
+	"msiof3_sync_b",
+	"msiof3_ss1_b",
+	"msiof3_ss2_b",
+	"msiof3_txd_b",
+	"msiof3_rxd_b",
+	"msiof3_clk_c",
+	"msiof3_sync_c",
+	"msiof3_txd_c",
+	"msiof3_rxd_c",
+	"msiof3_clk_d",
+	"msiof3_sync_d",
+	"msiof3_ss1_d",
+	"msiof3_txd_d",
+	"msiof3_rxd_d",
+};
+
+static const char * const scif0_groups[] = {
+	"scif0_data",
+	"scif0_clk_b",
+};
+
+static const char * const scif1_groups[] = {
+	"scif1_data_a",
+	"scif1_clk",
+	"scif1_ctrl",
+	"scif1_data_b",
+};
+
+static const char * const scif2_groups[] = {
+	"scif2_data",
+	"scif2_clk",
+};
+
+static const char * const scif3_groups[] = {
+	"scif3_data_a",
+	"scif3_clk",
+	"scif3_ctrl",
+	"scif3_data_b",
+};
+
+static const char * const scif4_groups[] = {
+	"scif4_data_a",
+	"scif4_clk_a",
+	"scif4_ctrl_a",
+	"scif4_data_b",
+	"scif4_clk_b",
+	"scif4_ctrl_b",
+	"scif4_data_c",
+	"scif4_clk_c",
+	"scif4_ctrl_c",
+};
+
+static const char * const scif5_groups[] = {
+	"scif5_data",
+	"scif5_clk",
+};
+
+static const char * const sdhi0_groups[] = {
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_ctrl",
+	"sdhi0_cd",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_data1",
+	"sdhi1_data4",
+	"sdhi1_ctrl",
+	"sdhi1_cd",
+	"sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+	"sdhi2_data1",
+	"sdhi2_data4",
+	"sdhi2_data8",
+	"sdhi2_ctrl",
+	"sdhi2_cd_a",
+	"sdhi2_wp_a",
+	"sdhi2_cd_b",
+	"sdhi2_wp_b",
+	"sdhi2_ds",
+};
+
+static const char * const sdhi3_groups[] = {
+	"sdhi3_data1",
+	"sdhi3_data4",
+	"sdhi3_data8",
+	"sdhi3_ctrl",
+	"sdhi3_cd",
+	"sdhi3_wp",
+	"sdhi3_ds",
+};
+
+static const char * const usb0_groups[] = {
+	"usb0",
+};
+
+static const char * const usb1_groups[] = {
+	"usb1",
+};
+
+static const char * const usb2_groups[] = {
+	"usb2",
+};
+
+static const char * const usb30_groups[] = {
+	"usb30",
+};
+
+static const char * const usb31_groups[] = {
+	"usb31",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(avb),
+	SH_PFC_FUNCTION(du),
+	SH_PFC_FUNCTION(hdmi0),
+	SH_PFC_FUNCTION(hdmi1),
+	SH_PFC_FUNCTION(msiof0),
+	SH_PFC_FUNCTION(msiof1),
+	SH_PFC_FUNCTION(msiof2),
+	SH_PFC_FUNCTION(msiof3),
+	SH_PFC_FUNCTION(scif0),
+	SH_PFC_FUNCTION(scif1),
+	SH_PFC_FUNCTION(scif2),
+	SH_PFC_FUNCTION(scif3),
+	SH_PFC_FUNCTION(scif4),
+	SH_PFC_FUNCTION(scif5),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(sdhi3),
+	SH_PFC_FUNCTION(usb0),
+	SH_PFC_FUNCTION(usb1),
+	SH_PFC_FUNCTION(usb2),
+	SH_PFC_FUNCTION(usb30),
+	SH_PFC_FUNCTION(usb31),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_0_15_FN, FN_IP7_11_8,
+		GP_0_14_FN, FN_IP7_7_4,
+		GP_0_13_FN, FN_IP7_3_0,
+		GP_0_12_FN, FN_IP6_31_28,
+		GP_0_11_FN, FN_IP6_27_24,
+		GP_0_10_FN, FN_IP6_23_20,
+		GP_0_9_FN, FN_IP6_19_16,
+		GP_0_8_FN, FN_IP6_15_12,
+		GP_0_7_FN, FN_IP6_11_8,
+		GP_0_6_FN, FN_IP6_7_4,
+		GP_0_5_FN, FN_IP6_3_0,
+		GP_0_4_FN, FN_IP5_31_28,
+		GP_0_3_FN, FN_IP5_27_24,
+		GP_0_2_FN, FN_IP5_23_20,
+		GP_0_1_FN, FN_IP5_19_16,
+		GP_0_0_FN, FN_IP5_15_12, }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_27_FN, FN_IP5_11_8,
+		GP_1_26_FN, FN_IP5_7_4,
+		GP_1_25_FN, FN_IP5_3_0,
+		GP_1_24_FN, FN_IP4_31_28,
+		GP_1_23_FN, FN_IP4_27_24,
+		GP_1_22_FN, FN_IP4_23_20,
+		GP_1_21_FN, FN_IP4_19_16,
+		GP_1_20_FN, FN_IP4_15_12,
+		GP_1_19_FN, FN_IP4_11_8,
+		GP_1_18_FN, FN_IP4_7_4,
+		GP_1_17_FN, FN_IP4_3_0,
+		GP_1_16_FN, FN_IP3_31_28,
+		GP_1_15_FN, FN_IP3_27_24,
+		GP_1_14_FN, FN_IP3_23_20,
+		GP_1_13_FN, FN_IP3_19_16,
+		GP_1_12_FN, FN_IP3_15_12,
+		GP_1_11_FN, FN_IP3_11_8,
+		GP_1_10_FN, FN_IP3_7_4,
+		GP_1_9_FN, FN_IP3_3_0,
+		GP_1_8_FN, FN_IP2_31_28,
+		GP_1_7_FN, FN_IP2_27_24,
+		GP_1_6_FN, FN_IP2_23_20,
+		GP_1_5_FN, FN_IP2_19_16,
+		GP_1_4_FN, FN_IP2_15_12,
+		GP_1_3_FN, FN_IP2_11_8,
+		GP_1_2_FN, FN_IP2_7_4,
+		GP_1_1_FN, FN_IP2_3_0,
+		GP_1_0_FN, FN_IP1_31_28, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_2_14_FN, FN_IP0_23_20,
+		GP_2_13_FN, FN_IP0_19_16,
+		GP_2_12_FN, FN_IP0_15_12,
+		GP_2_11_FN, FN_IP0_11_8,
+		GP_2_10_FN, FN_IP0_7_4,
+		GP_2_9_FN, FN_IP0_3_0,
+		GP_2_8_FN, FN_IP1_27_24,
+		GP_2_7_FN, FN_IP1_23_20,
+		GP_2_6_FN, FN_IP1_19_16,
+		GP_2_5_FN, FN_IP1_15_12,
+		GP_2_4_FN, FN_IP1_11_8,
+		GP_2_3_FN, FN_IP1_7_4,
+		GP_2_2_FN, FN_IP1_3_0,
+		GP_2_1_FN, FN_IP0_31_28,
+		GP_2_0_FN, FN_IP0_27_24, }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_3_15_FN, FN_IP10_23_20,
+		GP_3_14_FN, FN_IP10_19_16,
+		GP_3_13_FN, FN_IP10_15_12,
+		GP_3_12_FN, FN_IP10_11_8,
+		GP_3_11_FN, FN_IP8_31_28,
+		GP_3_10_FN, FN_IP8_27_24,
+		GP_3_9_FN, FN_IP8_23_20,
+		GP_3_8_FN, FN_IP8_19_16,
+		GP_3_7_FN, FN_IP8_15_12,
+		GP_3_6_FN, FN_IP8_11_8,
+		GP_3_5_FN, FN_IP8_7_4,
+		GP_3_4_FN, FN_IP8_3_0,
+		GP_3_3_FN, FN_IP7_31_28,
+		GP_3_2_FN, FN_IP7_27_24,
+		GP_3_1_FN, FN_IP7_23_20,
+		GP_3_0_FN, FN_IP7_19_16, }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_17_FN, FN_SD3_DS_MMC1_DS,
+		GP_4_16_FN, FN_IP10_7_4,
+		GP_4_15_FN, FN_IP10_3_0,
+		GP_4_14_FN, FN_IP9_31_28,
+		GP_4_13_FN, FN_IP9_27_24,
+		GP_4_12_FN, FN_SD3_DAT3_MMC1_DAT3,
+		GP_4_11_FN, FN_SD3_DAT2_MMC1_DAT2,
+		GP_4_10_FN, FN_SD3_DAT1_MMC1_DAT1,
+		GP_4_9_FN, FN_SD3_DAT0_MMC1_DAT0,
+		GP_4_8_FN, FN_SD3_CMD_MMC1_CMD,
+		GP_4_7_FN, FN_SD3_CLK_MMC1_CLK,
+		GP_4_6_FN, FN_IP9_23_20,
+		GP_4_5_FN, FN_IP9_19_16,
+		GP_4_4_FN, FN_IP9_15_12,
+		GP_4_3_FN, FN_IP9_11_8,
+		GP_4_2_FN, FN_IP9_7_4,
+		GP_4_1_FN, FN_SD2_CMD_MMC0_CMD,
+		GP_4_0_FN, FN_IP9_3_0, }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0,
+		GP_5_25_FN, FN_IP13_19_16,
+		GP_5_24_FN, FN_IP13_15_12,
+		GP_5_23_FN, FN_IP13_11_8,
+		GP_5_22_FN, FN_MSIOF0_RXD,
+		GP_5_21_FN, FN_IP13_7_4,
+		GP_5_20_FN, FN_MSIOF0_TXD,
+		GP_5_19_FN, FN_IP13_3_0,
+		GP_5_18_FN, FN_IP12_31_28,
+		GP_5_17_FN, FN_MSIOF0_SCK,
+		GP_5_16_FN, FN_IP12_27_24,
+		GP_5_15_FN, FN_IP12_23_20,
+		GP_5_14_FN, FN_IP12_19_16,
+		GP_5_13_FN, FN_IP12_15_12,
+		GP_5_12_FN, FN_IP12_11_8,
+		GP_5_11_FN, FN_IP12_7_4,
+		GP_5_10_FN, FN_IP12_3_0,
+		GP_5_9_FN, FN_IP11_31_28,
+		GP_5_8_FN, FN_IP11_27_24,
+		GP_5_7_FN, FN_IP11_23_20,
+		GP_5_6_FN, FN_IP11_19_16,
+		GP_5_5_FN, FN_IP11_15_12,
+		GP_5_4_FN, FN_IP11_11_8,
+		GP_5_3_FN, FN_IP11_7_4,
+		GP_5_2_FN, FN_IP11_3_0,
+		GP_5_1_FN, FN_IP10_31_28,
+		GP_5_0_FN, FN_IP10_27_24, }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+		GP_6_31_FN, FN_IP17_7_4,
+		GP_6_30_FN, FN_IP17_3_0,
+		GP_6_29_FN, FN_IP16_31_28,
+		GP_6_28_FN, FN_IP16_27_24,
+		GP_6_27_FN, FN_IP16_23_20,
+		GP_6_26_FN, FN_IP16_19_16,
+		GP_6_25_FN, FN_IP16_15_12,
+		GP_6_24_FN, FN_IP16_11_8,
+		GP_6_23_FN, FN_IP16_7_4,
+		GP_6_22_FN, FN_IP16_3_0,
+		GP_6_21_FN, FN_IP15_31_28,
+		GP_6_20_FN, FN_IP15_27_24,
+		GP_6_19_FN, FN_IP15_23_20,
+		GP_6_18_FN, FN_IP15_19_16,
+		GP_6_17_FN, FN_IP15_15_12,
+		GP_6_16_FN, FN_IP15_11_8,
+		GP_6_15_FN, FN_IP15_7_4,
+		GP_6_14_FN, FN_IP15_3_0,
+		GP_6_13_FN, FN_SSI_SDATA5,
+		GP_6_12_FN, FN_SSI_WS5,
+		GP_6_11_FN, FN_SSI_SCK5,
+		GP_6_10_FN, FN_IP14_31_28,
+		GP_6_9_FN, FN_IP14_27_24,
+		GP_6_8_FN, FN_IP14_23_20,
+		GP_6_7_FN, FN_IP14_19_16,
+		GP_6_6_FN, FN_IP14_15_12,
+		GP_6_5_FN, FN_IP14_11_8,
+		GP_6_4_FN, FN_IP14_7_4,
+		GP_6_3_FN, FN_IP14_3_0,
+		GP_6_2_FN, FN_IP13_31_28,
+		GP_6_1_FN, FN_IP13_27_24,
+		GP_6_0_FN, FN_IP13_23_20, }
+	},
+	{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_3_FN, FN_HDMI1_CEC,
+		GP_7_2_FN, FN_HDMI0_CEC,
+		GP_7_1_FN, FN_AVS2,
+		GP_7_0_FN, FN_AVS1, }
+	},
+	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+		/* IP0_31_28 [4] */
+		FN_IRQ1, FN_QPOLA, 0, FN_DU_DISP,
+		FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP0_27_24 [4] */
+		FN_IRQ0, FN_QPOLB, 0, FN_DU_CDE,
+		FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP0_23_20 [4] */
+		FN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4_N_TANS_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP0_19_16 [4] */
+		FN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4_N_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP0_15_12 [4] */
+		FN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP0_11_8 [4] */
+		FN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP0_7_4 [4] */
+		FN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP0_3_0 [4] */
+		FN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+		/* IP1_31_28 [4] */
+		FN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0,
+		FN_VI4_DATA8, 0, FN_DU_DB0, 0,
+		0, FN_PWM3_A, 0, 0,
+		0, 0, 0, 0,
+		/* IP1_27_24 [4] */
+		FN_PWM2_A, 0, 0, FN_HTX3_D,
+		0, 0, 0, 0,
+		0, FN_IETX_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP1_23_20 [4] */
+		FN_PWM1_A, 0, 0, FN_HRX3_D,
+		FN_VI4_DATA7_B, 0, 0, 0,
+		0, FN_IERX_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP1_19_16 [4] */
+		FN_PWM0, FN_AVB_AVTP_PPS, 0, 0,
+		FN_VI4_DATA6_B, 0, 0, 0,
+		0, FN_IECLK_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP1_15_12 [4] */
+		FN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC,
+		FN_VI4_DATA5_B, 0, 0, 0,
+		0, FN_PWM6_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP1_11_8 [4] */
+		FN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC,
+		FN_VI4_DATA4_B, 0, 0, 0,
+		0, FN_PWM5_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP1_7_4 [4] */
+		FN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1,
+		FN_VI4_DATA3_B, 0, 0, 0,
+		0, FN_PWM4_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP1_3_0 [4] */
+		FN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE,
+		FN_VI4_DATA2_B, 0, 0, 0,
+		0, FN_PWM3_B, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+		/* IP2_31_28 [4] */
+		FN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B,
+		0, 0, 0, FN_SDA6_A,
+		FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP2_27_24 [4] */
+		FN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B,
+		FN_VI4_DATA15, FN_VI5_DATA15, FN_DU_DB7, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP2_23_20 [4] */
+		FN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B,
+		FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP2_19_16 [4] */
+		FN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B,
+		FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP2_15_12 [4] */
+		FN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0,
+		FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP2_11_8 [4] */
+		FN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0,
+		FN_VI4_DATA11, 0, FN_DU_DB3, 0,
+		0, FN_PWM6_A, 0, 0,
+		0, 0, 0, 0,
+		/* IP2_7_4 [4] */
+		FN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0,
+		FN_VI4_DATA10, 0, FN_DU_DB2, 0,
+		0, FN_PWM5_A, 0, 0,
+		0, 0, 0, 0,
+		/* IP2_3_0 [4] */
+		FN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0,
+		FN_VI4_DATA9, 0, FN_DU_DB1, 0,
+		0, FN_PWM4_A, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+		/* IP3_31_28 [4] */
+		FN_A16, FN_LCDOUT8, 0, 0,
+		FN_VI4_FIELD, 0, FN_DU_DG0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP3_27_24 [4] */
+		FN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0,
+		FN_HRTS4_N, FN_VI5_DATA11, FN_DU_DG7, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP3_23_20 [4] */
+		FN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0,
+		FN_HCTS4_N, FN_VI5_DATA10, FN_DU_DG6, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP3_19_16 [4] */
+		FN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0,
+		FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP3_15_12 [4] */
+		FN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0,
+		FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP3_11_8 [4] */
+		FN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B,
+		FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A,
+		FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP3_7_4 [4] */
+		FN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4_N_TANS_B,
+		0, FN_VI5_HSYNC_N, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP3_3_0 [4] */
+		FN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4_N_B,
+		0, FN_VI5_VSYNC_N, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+		/* IP4_31_28 [4] */
+		FN_RD_WR_N, 0, FN_MSIOF3_RXD_D, FN_TX3_A,
+		FN_HTX3_A, 0, 0, 0,
+		FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0,
+		0, 0, 0, 0,
+		/* IP4_27_24 [4] */
+		FN_RD_N, 0, FN_MSIOF3_SYNC_D, FN_RX3_A,
+		FN_HRX3_A, 0, 0, 0,
+		FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0,
+		0, 0, 0, 0,
+		/* IP4_23_20 [4] */
+		FN_BS_N, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3,
+		FN_HSCK3, 0, 0, 0,
+		FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0,
+		0, 0, 0, 0,
+		/* IP4_19_16 [4] */
+		FN_CS1_N_A26, 0, 0, 0,
+		0, FN_VI5_CLK, 0, FN_EX_WAIT0_B,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP4_15_12 [4] */
+		FN_CS0_N, 0, 0, 0,
+		0, FN_VI5_CLKENB, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP4_11_8 [4] */
+		FN_A19, FN_LCDOUT11, 0, 0,
+		FN_VI4_CLKENB, 0, FN_DU_DG3, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP4_7_4 [4] */
+		FN_A18, FN_LCDOUT10, 0, 0,
+		FN_VI4_HSYNC_N, 0, FN_DU_DG2, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP4_3_0 [4] */
+		FN_A17, FN_LCDOUT9, 0, 0,
+		FN_VI4_VSYNC_N, 0, FN_DU_DG1, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+		/* IP5_31_28 [4] */
+		FN_D4, FN_MSIOF2_SCK_B, 0, 0,
+		FN_VI4_DATA20, FN_VI5_DATA4, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP5_27_24 [4] */
+		FN_D3, 0, FN_MSIOF3_TXD_A, 0,
+		FN_VI4_DATA19, FN_VI5_DATA3, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP5_23_20 [4] */
+		FN_D2, 0, FN_MSIOF3_RXD_A, 0,
+		FN_VI4_DATA18, FN_VI5_DATA2, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP5_19_16 [4] */
+		FN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0,
+		FN_VI4_DATA17, FN_VI5_DATA1, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP5_15_12 [4] */
+		FN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0,
+		FN_VI4_DATA16, FN_VI5_DATA0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP5_11_8 [4] */
+		FN_EX_WAIT0_A, FN_QCLK, 0, 0,
+		FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP5_7_4 [4] */
+		FN_WE1_N, 0, FN_MSIOF3_SS1_D, FN_RTS3_N_TANS,
+		FN_HRTS3_N, 0, 0, FN_SDA6_B,
+		FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0,
+		0, 0, 0, 0,
+		/* IP5_3_0 [4] */
+		FN_WE0_N, 0, FN_MSIOF3_TXD_D, FN_CTS3_N,
+		FN_HCTS3_N, 0, 0, FN_SCL6_B,
+		FN_CAN_CLK, 0, FN_IECLK_A, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+		/* IP6_31_28 [4] */
+		FN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C,
+		FN_VI4_DATA4_A, 0, FN_DU_DR4, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP6_27_24 [4] */
+		FN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B,
+		FN_VI4_DATA3_A, FN_RTS4_N_TANS_C, FN_DU_DR3, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP6_23_20 [4] */
+		FN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B,
+		FN_VI4_DATA2_A, FN_CTS4_N_C, FN_DU_DR2, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP6_19_16 [4] */
+		FN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0,
+		FN_VI4_DATA1_A, 0, FN_DU_DR1, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP6_15_12 [4] */
+		FN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C,
+		FN_VI4_DATA0_A, 0, FN_DU_DR0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP6_11_8 [4] */
+		FN_D7, FN_MSIOF2_TXD_B, 0, 0,
+		FN_VI4_DATA23, FN_VI5_DATA7, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP6_7_4 [4] */
+		FN_D6, FN_MSIOF2_RXD_B, 0, 0,
+		FN_VI4_DATA22, FN_VI5_DATA6, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP6_3_0 [4] */
+		FN_D5, FN_MSIOF2_SYNC_B, 0, 0,
+		FN_VI4_DATA21, FN_VI5_DATA5, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+		/* IP7_31_28 [4] */
+		FN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0,
+		0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP7_27_24 [4] */
+		FN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0,
+		0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP7_23_20 [4] */
+		FN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0,
+		0, 0, FN_STP_IVCXO27_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP7_19_16 [4] */
+		FN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0,
+		0, 0, FN_STP_OPWM_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP7_15_12 [4] */
+		FN_FSCLKST, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP7_11_8 [4] */
+		FN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C,
+		FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP7_7_4 [4] */
+		FN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C,
+		FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP7_3_0 [4] */
+		FN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C,
+		FN_VI4_DATA5_A, 0, FN_DU_DR5, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+		/* IP8_31_28 [4] */
+		FN_SD1_DAT3, FN_SD2_DAT7_MMC0_DAT7, FN_MSIOF1_SS2_G, 0,
+		0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP8_27_24 [4] */
+		FN_SD1_DAT2, FN_SD2_DAT6_MMC0_DAT6, FN_MSIOF1_SS1_G, 0,
+		0, FN_TS_SDAT1_B, FN_STP_ISD_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP8_23_20 [4] */
+		FN_SD1_DAT1, FN_SD2_DAT5_MMC0_DAT5, FN_MSIOF1_TXD_G, 0,
+		0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP8_19_16 [4] */
+		FN_SD1_DAT0, FN_SD2_DAT4_MMC0_DAT4, FN_MSIOF1_RXD_G, 0,
+		0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP8_15_12 [4] */
+		FN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, 0,
+		0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP8_11_8 [4] */
+		FN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0,
+		0, FN_SIM0_CLK_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP8_7_4 [4] */
+		FN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0,
+		0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP8_3_0 [4] */
+		FN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0,
+		0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+		/* IP9_31_28 [4] */
+		FN_SD3_DAT5_MMC1_DAT5, FN_SD2_WP_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP9_27_24 [4] */
+		FN_SD3_DAT4_MMC1_DAT4, FN_SD2_CD_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP9_23_20 [4] */
+		FN_SD2_DS_MMC0_DS, 0, 0, 0,
+		0, 0, 0, 0,
+		FN_SATA_DEVSLP_B, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP9_19_16 [4] */
+		FN_SD2_DAT3_MMC0_DAT3, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP9_15_12 [4] */
+		FN_SD2_DAT2_MMC0_DAT2, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP9_11_8 [4] */
+		FN_SD2_DAT1_MMC0_DAT1, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP9_7_4 [4] */
+		FN_SD2_DAT0_MMC0_DAT0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP9_3_0 [4] */
+		FN_SD2_CLK_MMC0_CLK, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+		/* IP10_31_28 [4] */
+		FN_RX0, FN_HRX1_B, 0, 0,
+		0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_27_24 [4] */
+		FN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,
+		FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B,
+		0, FN_ADICHS2, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_23_20 [4] */
+		FN_SD1_WP, 0, 0, 0,
+		0, FN_SIM0_D_B, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_19_16 [4] */
+		FN_SD1_CD, 0, 0, 0,
+		0, FN_SIM0_CLK_B, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_15_12 [4] */
+		FN_SD0_WP, 0, 0, 0,
+		FN_SDA2_B, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_11_8 [4] */
+		FN_SD0_CD, 0, 0, 0,
+		FN_SCL2_B, FN_SIM0_RST_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_7_4 [4] */
+		FN_SD3_DAT7_MMC1_DAT7, FN_SD3_WP, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_3_0 [4] */
+		FN_SD3_DAT6_MMC1_DAT6, FN_SD3_CD, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+		/* IP11_31_28 [4] */
+		FN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0,
+		0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,
+		0, FN_ADICLK, 0, 0,
+		0, 0, 0, 0,
+		/* IP11_27_24 [4] */
+		FN_RTS1_N_TANS, FN_HRTS1_N_A, FN_MSIOF1_TXD_B, 0,
+		0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B,
+		0, FN_ADICHS0, 0, 0,
+		0, 0, 0, 0,
+		/* IP11_23_20 [4] */
+		FN_CTS1_N, FN_HCTS1_N_A, FN_MSIOF1_RXD_B, 0,
+		0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B,
+		0, FN_ADIDATA, 0, 0,
+		0, 0, 0, 0,
+		/* IP11_19_16 [4] */
+		FN_TX1_A, FN_HTX1_A, 0, 0,
+		0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP11_15_12 [4] */
+		FN_RX1_A, FN_HRX1_A, 0, 0,
+		0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP11_11_8 [4] */
+		FN_RTS0_N_TANS, FN_HRTS1_N_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B,
+		FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B,
+		0, FN_ADICHS1, 0, 0,
+		0, 0, 0, 0,
+		/* IP11_7_4 [4] */
+		FN_CTS0_N, FN_HCTS1_N_B, FN_MSIOF1_SYNC_B, 0,
+		0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,
+		FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0,
+		0, 0, 0, 0,
+		/* IP11_3_0 [4] */
+		FN_TX0, FN_HTX1_B, 0, 0,
+		0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+		/* IP12_31_28 [4] */
+		FN_MSIOF0_SYNC, 0, 0, 0,
+		0, 0, 0, 0,
+		FN_AUDIO_CLKOUT_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP12_27_24 [4] */
+		FN_HRTS0_N, FN_TX2_B, FN_MSIOF1_SS1_D, 0,
+		FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A,
+		FN_AUDIO_CLKOUT2_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP12_23_20 [4] */
+		FN_HCTS0_N, FN_RX2_B, FN_MSIOF1_SYNC_D, 0,
+		FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D,
+		FN_RIF0_SYNC_C,
+		FN_AUDIO_CLKOUT1_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP12_19_16 [4] */
+		FN_HTX0, 0, FN_MSIOF1_TXD_D, 0,
+		FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP12_15_12 [4] */
+		FN_HRX0, 0, FN_MSIOF1_RXD_D, 0,
+		FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP12_11_8 [4] */
+		FN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A,
+		FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP12_7_4 [4] */
+		FN_RX2_A, 0, 0, FN_SD2_WP_B,
+		FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C,
+		0, FN_FSO_CFE_1_B, 0, 0,
+		0, 0, 0, 0,
+		/* IP12_3_0 [4] */
+		FN_TX2_A, 0, 0, FN_SD2_CD_B,
+		FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C,
+		0, FN_FSO_CFE_0_B, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+		/* IP13_31_28 [4] */
+		FN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP13_27_24 [4] */
+		FN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP13_23_20 [4] */
+		FN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP13_19_16 [4] */
+		FN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP13_15_12 [4] */
+		FN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0,
+		FN_SDA1_B, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP13_11_8 [4] */
+		FN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0,
+		FN_SCL1_B, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP13_7_4 [4] */
+		FN_MSIOF0_SS2, FN_TX5, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,
+		FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0,
+		FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0,
+		0, 0, 0, 0,
+		/* IP13_3_0 [4] */
+		FN_MSIOF0_SS1, FN_RX5, 0, FN_AUDIO_CLKA_C,
+		FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0,
+		FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+		/* IP14_31_28 [4] */
+		FN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0,
+		0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A,
+		FN_RIF2_D1_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP14_27_24 [4] */
+		FN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0,
+		0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A,
+		FN_RIF2_SYNC_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP14_23_20 [4] */
+		FN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0,
+		0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,
+		FN_RIF2_CLK_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP14_19_16 [4] */
+		FN_SSI_SDATA3, FN_HRTS2_N_A, FN_MSIOF1_TXD_A, 0,
+		0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A,
+		FN_RIF2_D0_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP14_15_12 [4] */
+		FN_SSI_WS34, FN_HCTS2_N_A, FN_MSIOF1_SS2_A, 0,
+		0, 0, FN_STP_IVCXO27_0_A, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP14_11_8 [4] */
+		FN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0,
+		0, 0, FN_STP_OPWM_0_A, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP14_7_4 [4] */
+		FN_SSI_SDATA2_A, 0, 0, 0,
+		FN_SSI_SCK1_B, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP14_3_0 [4] */
+		FN_SSI_SDATA1_A, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+		/* IP15_31_28 [4] */
+		FN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A,
+		FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5,
+		0, 0, 0, 0, 0,
+		0, 0, 0,
+		/* IP15_27_24 [4] */
+		FN_SSI_SDATA8, FN_HRTS2_N_B, FN_MSIOF1_TXD_C, 0,
+		0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A,
+		FN_RIF3_D1_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP15_23_20 [4] */
+		FN_SSI_SDATA7, FN_HCTS2_N_B, FN_MSIOF1_RXD_C, 0,
+		0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A,
+		FN_RIF3_D0_A, 0, FN_TCLK2_A, 0,
+		0, 0, 0, 0,
+		/* IP15_19_16 [4] */
+		FN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0,
+		0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,
+		FN_RIF3_SYNC_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP15_15_12 [4] */
+		FN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0,
+		0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A,
+		FN_RIF3_CLK_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP15_11_8 [4] */
+		FN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D,
+		0, 0, 0, 0,
+		FN_SATA_DEVSLP_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP15_7_4 [4] */
+		FN_SSI_WS6, FN_USB2_OVC, 0, FN_SIM0_D_D,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP15_3_0 [4] */
+		FN_SSI_SCK6, FN_USB2_PWEN, 0, FN_SIM0_RST_D,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+		/* IP16_31_28 [4] */
+		FN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B,
+		FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D,
+		FN_STP_IVCXO27_0_E,
+		FN_RIF3_D1_B, 0, FN_FSO_TOE_B, FN_TPU0TO1,
+		0, 0, 0, 0,
+		/* IP16_27_24 [4] */
+		FN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B,
+		FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,
+		FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0,
+		0, 0, 0, 0,
+		/* IP16_23_20 [4] */
+		FN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0,
+		FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,
+		FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0,
+		0, 0, 0, 0,
+		/* IP16_19_16 [4] */
+		FN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C,
+		FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,
+		FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0,
+		0, 0, 0, 0,
+		/* IP16_15_12 [4] */
+		FN_USB0_OVC, 0, 0, FN_SIM0_D_C,
+		0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0,
+		FN_RIF3_SYNC_B, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP16_11_8 [4] */
+		FN_USB0_PWEN, 0, 0, FN_SIM0_RST_C,
+		0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,
+		FN_RIF3_CLK_B, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP16_7_4 [4] */
+		FN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0,
+		0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,
+		0, 0, FN_TCLK1_A, 0,
+		0, 0, 0, 0,
+		/* IP16_3_0 [4] */
+		FN_AUDIO_CLKA_A, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, FN_CC5_OSCOUT,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+		/* IP17_31_28 [4] */
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP17_27_24 [4] */
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP17_23_20 [4] */
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP17_19_16 [4] */
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP17_15_12 [4] */
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP17_11_8 [4] */
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP17_7_4 [4] */
+		FN_USB31_OVC, 0, 0, FN_AUDIO_CLKOUT3_B,
+		FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0,
+		FN_RIF2_D1_B, 0, 0, FN_TPU0TO3,
+		0, 0, 0, 0,
+		/* IP17_3_0 [4] */
+		FN_USB31_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B,
+		FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,
+		FN_RIF2_D0_B, 0, 0, FN_TPU0TO2,
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
+			     1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
+			     2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
+		/* RESERVED [1] */
+		0, 0,
+		/* SEL_MSIOF3 [2] */
+		FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
+		FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
+		/* SEL_MSIOF2 [2] */
+		FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
+		FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
+		/* SEL_MSIOF1 [3] */
+		FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
+		FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
+		FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
+		FN_SEL_MSIOF1_6, FN_SEL_MSIOF1_7,
+		/* SEL_LBSC [1] */
+		FN_SEL_LBSC_0, FN_SEL_LBSC_1,
+		/* SEL_IEBUS [1] */
+		FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
+		/* SEL_I2C6 [2] */
+		FN_SEL_I2C6_0, FN_SEL_I2C6_1,
+		FN_SEL_I2C6_2, FN_SEL_I2C6_3,
+		/* SEL_I2C2 [1] */
+		FN_SEL_I2C2_0, FN_SEL_I2C2_1,
+		/* SEL_I2C1 [1] */
+		FN_SEL_I2C1_0, FN_SEL_I2C1_1,
+		/* SEL_HSCIF4 [1] */
+		FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
+		/* SEL_HSCIF3 [2] */
+		FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
+		FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
+		/* SEL_HSCIF2 [1] */
+		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+		/* SEL_HSCIF1 [1] */
+		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+		/* SEL_FSO [1] */
+		FN_SEL_FSO_0, FN_SEL_FSO_1,
+		/* SEL_FM [1] */
+		FN_SEL_FM_0, FN_SEL_FM_1,
+		/* SEL_ETHERAVB [1] */
+		FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
+		/* SEL_DRIF1 [2] */
+		FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
+		FN_SEL_DRIF1_2, FN_SEL_DRIF1_3,
+		/* SEL_DRIF0 [2] */
+		FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
+		FN_SEL_DRIF0_2, FN_SEL_DRIF0_3,
+		/* SEL_DRIF0 [1] */
+		FN_SEL_CANFD0_0, FN_SEL_CANFD0_1,
+		/* SEL_DRIF0 [2] */
+		FN_SEL_ADG_0, FN_SEL_ADG_1,
+		FN_SEL_ADG_2, FN_SEL_ADG_3,
+		/* RESERVED [1] */
+		0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
+			     2, 3, 1, 2, 3, 1, 1, 2, 1,
+			     2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+		/* SEL_TSIF1 [1] */
+		FN_SEL_TSIF1_0, FN_SEL_TSIF1_1,
+		FN_SEL_TSIF1_2, FN_SEL_TSIF1_3,
+		/* SEL_TSIF0 [3] */
+		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
+		FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+		FN_SEL_TSIF0_4, FN_SEL_TSIF0_5,
+		FN_SEL_TSIF0_6, FN_SEL_TSIF0_7,
+		/* SEL_TIMER_TMU [1] */
+		FN_SEL_TIMER_TMU_0, FN_SEL_TIMER_TMU_1,
+		/* SEL_SSP1_1 [2] */
+		FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1,
+		FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3,
+		/* SEL_SSP1_0 [3] */
+		FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,
+		FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3,
+		FN_SEL_SSP1_0_4, FN_SEL_SSP1_0_5,
+		FN_SEL_SSP1_0_6, FN_SEL_SSP1_0_7,
+		/* SEL_SSI [1] */
+		FN_SEL_SSI_0, FN_SEL_SSI_1,
+		/* SEL_SPEED_PULSE [1] */
+		FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,
+		/* SEL_SIMCARD [2] */
+		FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1,
+		FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,
+		/* SEL_SDHI2 [1] */
+		FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
+		/* SEL_SCIF4 [2] */
+		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
+		FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+		/* SEL_SCIF3 [1] */
+		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+		/* SEL_SCIF2 [1] */
+		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
+		/* SEL_SCIF1 [1] */
+		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
+		/* SEL_SCIF [1] */
+		FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+		/* SEL_REMOCON [1] */
+		FN_SEL_REMOCON_0, FN_SEL_REMOCON_1,
+		/* RESERVED [2] */
+		0, 0, 0, 0,
+		/* SEL_RCAN0 [1] */
+		FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
+		/* SEL_PWM6 [1] */
+		FN_SEL_PWM6_0, FN_SEL_PWM6_1,
+		/* SEL_PWM5 [1] */
+		FN_SEL_PWM5_0, FN_SEL_PWM5_1,
+		/* SEL_PWM4 [1] */
+		FN_SEL_PWM4_0, FN_SEL_PWM4_1,
+		/* SEL_PWM3 [1] */
+		FN_SEL_PWM3_0, FN_SEL_PWM3_1,
+		/* SEL_PWM2 [1] */
+		FN_SEL_PWM2_0, FN_SEL_PWM2_1,
+		/* SEL_PWM1 [1] */
+		FN_SEL_PWM1_0, FN_SEL_PWM1_1, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
+			     1, 1, 1, 1, 4, 4, 4,
+			     4, 4, 4, 1, 2, 1) {
+		/* I2C_SEL_5 [1] */
+		FN_I2C_SEL_5_0, FN_I2C_SEL_5_1,
+		/* I2C_SEL_3 [1] */
+		FN_I2C_SEL_3_0, FN_I2C_SEL_3_1,
+		/* I2C_SEL_0 [1] */
+		FN_I2C_SEL_0_0, FN_I2C_SEL_0_1,
+		/* RESERVED [1] */
+		0, 0,
+		/* RESERVED [4] */
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		/* RESERVED [4] */
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		/* RESERVED [4] */
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		/* RESERVED [4] */
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		/* RESERVED [4] */
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		/* RESERVED [4] */
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		/* RESERVED [1] */
+		0, 0,
+		/* SEL_VSP [1] */
+		FN_SEL_VSP_0, FN_SEL_VSP_1,
+		FN_SEL_VSP_2, FN_SEL_VSP_3,
+		/* SEL_VIN4 [1] */
+		FN_SEL_VIN4_0, FN_SEL_VIN4_1, }
+	},
+
+	{ },
+};
+
+const struct sh_pfc_soc_info r8a7795_pinmux_info = {
+	.name = "r8a77950_pfc",
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
+
+	.cfg_regs = pinmux_config_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
-- 
1.9.1

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