linux-kernel - Re: [LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq MPSoC GQSPI controller

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Date:	Wed, 26 Aug 2015 08:56:22 +0200
From:	Marek Vasut <marex@...x.de>
To:	Ranjit Waghmode <ranjit.waghmode@...inx.com>
Cc:	dwmw2@...radead.org, computersforpeace@...il.com,
	broonie@...nel.org, michal.simek@...inx.com,
	soren.brinkmann@...inx.com, zajec5@...il.com, ben@...adent.org.uk,
	b32955@...escale.com, knut.wohlrab@...bosch.com,
	juhosg@...nwrt.org, beanhuo@...ron.com,
	linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-spi@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	harinik@...inx.com, punnaia@...inx.com
Subject: Re: [LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq MPSoC GQSPI controller

On Wednesday, August 26, 2015 at 08:26:03 AM, Ranjit Waghmode wrote:
> This series adds dual parallel mode support for Zynq Ultrascale+
> MPSoC GQSPI controller driver.
> 
> What is dual parallel mode?
> ---------------------------
> ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities: 1) Supporting two SPI flash memories operating in
> parallel. 8 I/O lines. 2) Chip selects and clock are shared to both the
> flash devices
> 3) This mode is targeted for faster read/write speed and also doubles the
> size 4) Commands/data can be transmitted/received from both the
> devices(mirror), or only upper or only lower flash memory devices.
> 5) Data arrangement:
>    With stripe enabled,
>    Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
>    Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.

This might be a dumb question, but why don't you just treat this as an
SPI NOR flash with 8-bit bus ?

Best regards,
Marek Vasut
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