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Message-ID: <55E07A4E.1070309@imgtec.com>
Date:	Fri, 28 Aug 2015 16:12:14 +0100
From:	Qais Yousef <qais.yousef@...tec.com>
To:	Thomas Gleixner <tglx@...utronix.de>
CC:	Marc Zyngier <marc.zyngier@....com>,
	"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
	Jason Cooper <jason@...edaemon.net>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mips@...ux-mips.org" <linux-mips@...ux-mips.org>,
	Mark Rutland <Mark.Rutland@....com>,
	Jiang Liu <jiang.liu@...ux.intel.com>,
	Mark Brown <broonie@...nel.org>,
	Lisa Parratt <Lisa.Parratt@...tec.com>
Subject: Re: [PATCH 01/10] irqchip: irq-mips-gic: export gic_send_ipi

On 08/28/2015 03:22 PM, Thomas Gleixner wrote:
>>>      To configure your coprocessor proper, we need a translation
>>>      mechanism from the linux interrupt number to the magic value which
>>>      needs to be written into the trigger register when the coprocessor
>>>      wants to send an interrupt or an IPI.
>>>
>>>      int irq_get_irq_hwcfg(unsigned int irq, struct irq_hwcfg *cfg);
>>>
>>>      struct irq_hwcfg needs to be defined, but it might look like this:
>>>
>>>        {
>>> 	/* Generic fields */
>>> 	x;
>>> 	...
>>> 	union {
>>> 	      mips_gic;
>>> 	      ...
>>> 	};
>>>        };
> That function provides you the information which you have to hand over
> to your coprocessor firmware.
>
>

Of course!

* me slapping myself on the back *

Thanks,
Qais
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