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Message-ID: <55E654F4.4000306@rock-chips.com>
Date: Wed, 02 Sep 2015 09:46:28 +0800
From: Yakir Yang <ykk@...k-chips.com>
To: Heiko Stuebner <heiko@...ech.de>
CC: Thierry Reding <treding@...dia.com>,
Jingoo Han <jingoohan1@...il.com>,
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Subject: Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
Hi Heiko,
在 09/02/2015 04:58 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> small nit more below
>
> Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
>> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>>> +- clocks: from common clock binding: handle to dp clock.
>>> + of memory mapped region.
>>> +- clock-names: from common clock binding:
>>> + Required elements: "sclk_dp" "sclk_dp_24m"
>>> +
>>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>>> +- #phy-cells : from the generic PHY bindings, must be 0;
>>> +
>>> +Example:
>>> +
>>> +edp_phy: phy@...70274 {
>> edp_phy: edp-phy {
>>
>>> + compatilble = "rockchip,rk3288-dp-phy";
> typo: compatible
Aha, thanks.
- Yakir
>
>
>
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