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Message-ID: <20150908133240.GE9751@sirena.org.uk>
Date:	Tue, 8 Sep 2015 14:32:40 +0100
From:	Mark Brown <broonie@...nel.org>
To:	Linus Walleij <linus.walleij@...aro.org>
Cc:	Bjorn Andersson <bjorn.andersson@...ymobile.com>,
	Alexandre Courbot <gnurou@...il.com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Mark Rutland <mark.rutland@....com>,
	Pawel Moll <pawel.moll@....com>,
	Rob Herring <robh+dt@...nel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/4] Qualcomm Shared Memory State Machines

On Tue, Sep 08, 2015 at 02:20:14PM +0200, Linus Walleij wrote:
> On Thu, Aug 27, 2015 at 7:37 PM, Bjorn Andersson
> <bjorn.andersson@...ymobile.com> wrote:

> Let's discuss this a bit, looping in Mark Brown.

Please don't send upstream discussions ot my work address.

> While sparsely documented: what about regmap (maybe in the
> form of syscon) and drivers/base/regmap/regmap-irq.c for the
> interrupt handling?

> I cannot claim to understand regmap-irq.c, but I just intuitively
> think it deserves consideration, such that drivers who need one
> of these misc registers can read/write their bits with regmap
> accessors and also get IRQs by way of regmap-irq.

Well, all it's doing is exporting a simple register based interrupt
controller based on regmap.  There's not a lot to document.  If you're
using it with a system controller you'd probably want to implement
support for handling interrupts directly in the primary handler rather
than using a threaded handler.  Alternatively if there's no cache or no
overlap between interrupt registers and other registers then just using
the genirq MMIO code should do the trick.

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