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Message-ID: <CAFcVECJ_sF6Sav4NffMkwS5iQnPk2x7SE=qji5ByF17ejX0n=g@mail.gmail.com>
Date: Fri, 11 Sep 2015 21:54:29 +0530
From: Harini Katakam <harinikatakamlinux@...il.com>
To: Mark Brown <broonie@...nel.org>
Cc: Ranjit Abhimanyu Waghmode <ranjit.waghmode@...inx.com>,
"dwmw2@...radead.org" <dwmw2@...radead.org>,
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Soren Brinkmann <sorenb@...inx.com>,
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<linux-arm-kernel@...ts.infradead.org>,
Punnaiah Choudary Kalluri <punnaia@...inx.com>
Subject: Re: [LINUX RFC v2 1/4] spi: add support of two chip selects & data stripe
Hi Mark,
On Fri, Sep 11, 2015 at 6:06 PM, Mark Brown <broonie@...nel.org> wrote:
> On Fri, Sep 04, 2015 at 12:02:21PM +0000, Ranjit Abhimanyu Waghmode wrote:
>
> Please fix your mail client to word wrap within paragraphs and to quote
> text without reflowing it - your messages are very hard to read.
>
>> > > + /* Controller may support more than one chip.
>> > > + * This flag will enable that feature.
>> > > + */
>> > > +#define SPI_MASTER_BOTH_CS BIT(8) /* enable both
>> > chips */
>
>> Now we can consider following use cases:
>
>> Suppose we need to send the same data to multiple slaves of same kind:
>> Here the application need not to do individual slave access for writing, instead it can send data to all the devices in one go.
>
> That's a *very* specific application which will only work for write only
> devices - I'd be surprised if such systems actually had distinct chip
> select lines at the CPU level.
>
Agreed that it is very specific but here are a few ways it is used
when communicating with two flash devices in parallel configuration:
- Write enable is sent to both devices using a single operation.
- Writing to any configuration registers in the flash is done in one go
- Some application that want to mirror important data to both devices.
Even with reading, the assertion of multiple cs combined with stripe
will mean:
- Two status bytes, one form each will be obtained in one operation
- Similarly data that was written using stripe is read back and combined.
Such systems could still maintain separate chip selects to perform
individual operations such as reading flash ID, debugging failures or
locking specific sectors.
Regards,
Harini
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