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Message-Id: <1442476272-31723-1-git-send-email-wxt@rock-chips.com>
Date:	Thu, 17 Sep 2015 15:51:09 +0800
From:	Caesar Wang <wxt@...k-chips.com>
To:	Heiko Stuebner <heiko@...ech.de>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>
Cc:	Caesar Wang <wxt@...k-chips.com>, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
	Kumar Gala <galak@...eaurora.org>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	linux-rockchip@...ts.infradead.org,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Olof Johansson <olof@...om.net>,
	Mark Rutland <mark.rutland@....com>,
	linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 0/3] Support the timer on RK3368 SoC

Timer0~11 count up from zero to a programmed value and
generate an interrupt when the count reaches the programmed value.

TIMER0, TIMER1, TIMER2, Timer3, TIMER4 and TIMER5 are in the CPU
subsystem, using timer ch0 ~ ch5 respectively. The timer clock is 24MHz
OSC.

This series are found on RK3368 SoC, verified on rk3368 evb board.



Caesar Wang (3):
  clocksource: rockchip: Make the driver more readability and compatible
  arm64: Enable the timer on Rockchip architecture
  arm64: dts: rockchip: Add the needed timer for rk3368 SoC

 arch/arm64/Kconfig.platforms             |  1 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi |  6 ++++++
 drivers/clocksource/rockchip_timer.c     | 29 +++++++++++++++--------------
 3 files changed, 22 insertions(+), 14 deletions(-)

-- 
1.9.1

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