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Message-Id: <1442476272-31723-4-git-send-email-wxt@rock-chips.com>
Date:	Thu, 17 Sep 2015 15:51:12 +0800
From:	Caesar Wang <wxt@...k-chips.com>
To:	Heiko Stuebner <heiko@...ech.de>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>
Cc:	Caesar Wang <wxt@...k-chips.com>, devicetree@...r.kernel.org,
	Kumar Gala <galak@...eaurora.org>,
	linux-kernel@...r.kernel.org,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	linux-rockchip@...ts.infradead.org,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Olof Johansson <olof@...om.net>,
	linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 3/3] arm64: dts: rockchip: Add the needed timer for rk3368 SoC

There is a need of a broadcast timer in this case to ensure proper
wakeup when the cpus are in sleep mode and a timer expires.

Signed-off-by: Caesar Wang <wxt@...k-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a712bea..99edbaa 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -214,6 +214,12 @@
 			(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	timer@...10000 {
+		compatible = "rockchip,rk3288-timer";
+		reg = <0x0 0xff810000 0x0 0x20>;
+		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	xin24m: oscillator {
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
-- 
1.9.1

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