linux-kernel - [tip:perf/core] perf/x86/intel: Fix Skylake FRONTEND MSR extrareg mask

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Message-ID: <tip-dfe1f3cb312624928052413928d88b0ee3492216@git.kernel.org>
Date:	Fri, 18 Sep 2015 01:46:50 -0700
From:	tip-bot for Andi Kleen <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	peterz@...radead.org, linux-kernel@...r.kernel.org, hpa@...or.com,
	mingo@...nel.org, eranian@...gle.com,
	torvalds@...ux-foundation.org, ak@...ux.intel.com,
	tglx@...utronix.de
Subject: [tip:perf/core] perf/x86/intel:
  Fix Skylake FRONTEND MSR extrareg mask

Commit-ID:  dfe1f3cb312624928052413928d88b0ee3492216
Gitweb:     http://git.kernel.org/tip/dfe1f3cb312624928052413928d88b0ee3492216
Author:     Andi Kleen <ak@...ux.intel.com>
AuthorDate: Wed, 9 Sep 2015 14:54:00 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Fri, 18 Sep 2015 09:20:23 +0200

perf/x86/intel: Fix Skylake FRONTEND MSR extrareg mask

Stephane pointed out that the extrareg mask was one bit too short.
The bubble width field was truncated by one bit. Fix that here.
Also add some extra comments on the reserved bits inside the event
select code.

Reported-by: Stephane Eranian <eranian@...gle.com>
Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Acked-by: Thomas Gleixner <tglx@...utronix.de>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Link: http://lkml.kernel.org/r/1441835640-21347-3-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index ef74c9d..f63360b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -205,7 +205,11 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
-	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x3fff17, FE),
+	/*
+	 * Note the low 8 bits eventsel code is not a continuous field, containing
+	 * some #GPing bits. These are masked out.
+	 */
+	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 	EVENT_EXTRA_END
 };
 
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