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Message-ID: <20150920041620.GD3039@x1>
Date: Sun, 20 Sep 2015 05:16:20 +0100
From: Lee Jones <lee.jones@...aro.org>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: linux-kernel@...r.kernel.org,
Mika Westerberg <mika.westerberg@...ux.intel.com>
Subject: Re: [PATCH v1 2/2] mfd: intel-lpss: use writeq() helper
On Mon, 14 Sep 2015, Andy Shevchenko wrote:
> There are already helper functions to do 64-bit I/O on 32-bit machines, thus we
> don't need to reinvent the wheel. In our case we can't use readq() / writeq()
> even on 64-bit kernel since there is a hardware limitation (OCP bus is a 32-bit
> bus).
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> ---
> drivers/mfd/intel-lpss.c | 12 ++++--------
> 1 file changed, 4 insertions(+), 8 deletions(-)
Applied, thanks.
> diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c
> index fdf4d5c..001a7d7 100644
> --- a/drivers/mfd/intel-lpss.c
> +++ b/drivers/mfd/intel-lpss.c
> @@ -26,6 +26,8 @@
> #include <linux/pm_runtime.h>
> #include <linux/seq_file.h>
>
> +#include <asm-generic/io-64-nonatomic-lo-hi.h>
> +
> #include "intel-lpss.h"
>
> #define LPSS_DEV_OFFSET 0x000
> @@ -52,8 +54,7 @@
> #define LPSS_PRIV_SSP_REG 0x20
> #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
>
> -#define LPSS_PRIV_REMAP_ADDR_LO 0x40
> -#define LPSS_PRIV_REMAP_ADDR_HI 0x44
> +#define LPSS_PRIV_REMAP_ADDR 0x40
>
> #define LPSS_PRIV_CAPS 0xfc
> #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
> @@ -250,12 +251,7 @@ static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
> {
> resource_size_t addr = lpss->info->mem->start;
>
> - writel(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR_LO);
> -#if BITS_PER_LONG > 32
> - writel(addr >> 32, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI);
> -#else
> - writel(0, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI);
> -#endif
> + lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
> }
>
> static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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