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Message-Id: <1442847678-7970-14-git-send-email-peter.senna@gmail.com>
Date: Mon, 21 Sep 2015 17:01:17 +0200
From: Peter Senna Tschudin <peter.senna@...il.com>
To: balbi@...com, stern@...land.harvard.edu,
sergei.shtylyov@...entembedded.com, standby24x7@...il.com,
pmladek@...e.cz, linux-usb@...r.kernel.org,
linux-kernel@...r.kernel.org, gregkh@...uxfoundation.org
Cc: Peter Senna Tschudin <peter.senna@...il.com>
Subject: [PATCH 13/14] RFC: usb/host/faraday-hcd: Move #defines outside struct
For making the code more readable and to facilitate supporting multiple
hardware versions, move #defines to outside the struct declaration. This
patch also renames fhcd2xx_regs to fotg210_regs as this struct is
specific to fotg210.
Signed-off-by: Peter Senna Tschudin <peter.senna@...il.com>
---
drivers/usb/host/faraday-hcd.h | 137 ++++++++++++++++++++++-------------------
1 file changed, 74 insertions(+), 63 deletions(-)
diff --git a/drivers/usb/host/faraday-hcd.h b/drivers/usb/host/faraday-hcd.h
index cf29edf..f75c467 100644
--- a/drivers/usb/host/faraday-hcd.h
+++ b/drivers/usb/host/faraday-hcd.h
@@ -85,7 +85,7 @@ struct fhcd2xx_hcd { /* one per controller */
/* glue to PCI and HCD framework */
struct fhcd2xx_caps __iomem *caps;
- struct fhcd2xx_regs __iomem *regs;
+ struct fotg210_regs __iomem *regs;
struct ehci_dbg_port __iomem *debug;
__u32 hcs_params; /* cached register copy */
@@ -221,84 +221,95 @@ struct fhcd2xx_caps {
u8 portroute[8]; /* nibbles for routing - offset 0xC */
};
-
-/* Section 2.3 Host Controller Operational Registers */
-struct fhcd2xx_regs {
-
- /* USBCMD: offset 0x00 */
- u32 command;
-
/* EHCI 1.1 addendum */
/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
-#define CMD_PARK (1<<11) /* enable "park" on async qh */
-#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
-#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
-#define CMD_ASE (1<<5) /* async schedule enable */
-#define CMD_PSE (1<<4) /* periodic schedule enable */
+#define CMD_PARK (1<<11) /* enable "park" on async qh */
+#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
+#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
+#define CMD_ASE (1<<5) /* async schedule enable */
+#define CMD_PSE (1<<4) /* periodic schedule enable */
+
/* 3:2 is periodic frame list size */
-#define CMD_RESET (1<<1) /* reset HC not bus */
-#define CMD_RUN (1<<0) /* start/stop HC */
+#define CMD_RESET (1<<1) /* reset HC not bus */
+#define CMD_RUN (1<<0) /* start/stop HC */
- /* USBSTS: offset 0x04 */
- u32 status;
-#define STS_ASS (1<<15) /* Async Schedule Status */
-#define STS_PSS (1<<14) /* Periodic Schedule Status */
-#define STS_RECL (1<<13) /* Reclamation */
-#define STS_HALT (1<<12) /* Not running (any reason) */
-/* some bits reserved */
- /* these STS_* flags are also intr_enable bits (USBINTR) */
-#define STS_IAA (1<<5) /* Interrupted on async advance */
-#define STS_FATAL (1<<4) /* such as some PCI access errors */
-#define STS_FLR (1<<3) /* frame list rolled over */
-#define STS_PCD (1<<2) /* port change detect */
-#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
-#define STS_INT (1<<0) /* "normal" completion (short, ...) */
+#define STS_ASS (1<<15) /* Async Schedule Status */
+#define STS_PSS (1<<14) /* Periodic Schedule Status */
+#define STS_RECL (1<<13) /* Reclamation */
+#define STS_HALT (1<<12) /* Not running (any reason) */
+
+/* some bits reserved
+ * these STS_* flags are also intr_enable bits (USBINTR)
+ */
+#define STS_IAA (1<<5) /* Interrupted on async advance */
+#define STS_FATAL (1<<4) /* such as some PCI access errors */
+#define STS_FLR (1<<3) /* frame list rolled over */
+#define STS_PCD (1<<2) /* port change detect */
+#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
+#define STS_INT (1<<0) /* "normal" completion (short, ...) */
- /* USBINTR: offset 0x08 */
- u32 intr_enable;
-
- /* FRINDEX: offset 0x0C */
- u32 frame_index; /* current microframe number */
- /* CTRLDSSEGMENT: offset 0x10 */
- u32 segment; /* address bits 63:32 if needed */
- /* PERIODICLISTBASE: offset 0x14 */
- u32 frame_list; /* points to periodic list */
- /* ASYNCLISTADDR: offset 0x18 */
- u32 async_next; /* address of next async queue head */
-
- u32 reserved1;
- /* PORTSC: offset 0x20 */
- u32 port_status;
/* 31:23 reserved */
-#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
-#define PORT_RESET (1<<8) /* reset port */
-#define PORT_SUSPEND (1<<7) /* suspend port */
-#define PORT_RESUME (1<<6) /* resume it */
-#define PORT_PEC (1<<3) /* port enable change */
-#define PORT_PE (1<<2) /* port enable */
-#define PORT_CSC (1<<1) /* connect status change */
-#define PORT_CONNECT (1<<0) /* device connected */
+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
+#define PORT_RESET (1<<8) /* reset port */
+#define PORT_SUSPEND (1<<7) /* suspend port */
+#define PORT_RESUME (1<<6) /* resume it */
+#define PORT_PEC (1<<3) /* port enable change */
+#define PORT_PE (1<<2) /* port enable */
+#define PORT_CSC (1<<1) /* connect status change */
+#define PORT_CONNECT (1<<0) /* device connected */
#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
- u32 reserved2[19];
- /* OTGCSR: offet 0x70 */
- u32 otgcsr;
+/* FOTG210 only: */
#define OTGCSR_HOST_SPD_TYP (3 << 22)
#define OTGCSR_A_BUS_DROP (1 << 5)
#define OTGCSR_A_BUS_REQ (1 << 4)
+#define OTGISR_OVC (1 << 10)
+#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
+#define GMIR_MHC_INT (1 << 2)
+#define GMIR_MOTG_INT (1 << 1)
+#define GMIR_MDEV_INT (1 << 0)
+
+/* Section 2.3 Host Controller Operational Registers */
+struct fotg210_regs {
+
+ /* USBCMD: offset 0x00 */
+ u32 command;
+
+ /* USBSTS: offset 0x04 */
+ u32 status;
+
+ /* USBINTR: offset 0x08 */
+ u32 intr_enable;
+
+ /* FRINDEX: offset 0x0C - current microframe number */
+ u32 frame_index;
+
+ /* CTRLDSSEGMENT: offset 0x10 - address bits 63:32 if needed */
+ u32 segment;
+
+ /* PERIODICLISTBASE: offset 0x14 - points to periodic list */
+ u32 frame_list;
+
+ /* ASYNCLISTADDR: offset 0x18 - address of next async queue head */
+ u32 async_next;
+
+ u32 reserved1;
+
+ /* PORTSC: offset 0x20 */
+ u32 port_status;
+
+ u32 reserved2[19];
+
+ /* OTGCSR: offet 0x70 */
+ u32 otgcsr;
/* OTGISR: offset 0x74 */
- u32 otgisr;
-#define OTGISR_OVC (1 << 10)
+ u32 otgisr;
- u32 reserved3[15];
+ u32 reserved3[15];
/* GMIR: offset 0xB4 */
- u32 gmir;
-#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
-#define GMIR_MHC_INT (1 << 2)
-#define GMIR_MOTG_INT (1 << 1)
-#define GMIR_MDEV_INT (1 << 0)
+ u32 gmir;
};
/*-------------------------------------------------------------------------*/
--
2.1.0
--
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