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Message-ID: <20150922224723.GB26335@jcartwri.amer.corp.natinst.com>
Date: Tue, 22 Sep 2015 17:47:23 -0500
From: Josh Cartwright <joshc@...com>
To: atull@...nsource.altera.com
Cc: gregkh@...uxfoundation.org, jgunthorpe@...idianresearch.com,
hpa@...or.com, monstr@...str.eu, michal.simek@...inx.com,
rdunlap@...radead.org, Moritz Fischer <moritz.fischer@...us.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
pantelis.antoniou@...sulko.com, robh+dt@...nel.org,
grant.likely@...aro.org, iws@...o.caltech.edu,
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Subject: Re: [PATCH v11 4/4] fpga manager: add driver for socfpga fpga manager
On Tue, Sep 22, 2015 at 10:21:11AM -0500, atull@...nsource.altera.com wrote:
> From: Alan Tull <atull@...nsource.altera.com>
>
> Add driver to fpga manager framework to allow configuration
> of FPGA in Altera SoCFPGA parts.
>
> Signed-off-by: Alan Tull <atull@...nsource.altera.com>
> Acked-by: Michal Simek <michal.simek@...inx.com>
> Acked-by: Moritz Fischer <moritz.fischer@...us.com>
[..]
> +++ b/drivers/fpga/Kconfig
> @@ -11,4 +11,14 @@ config FPGA
> kernel. The FPGA framework adds a FPGA manager class and FPGA
> manager drivers.
>
> +if FPGA
FPGA is unconditionally set here, otherwise drivers/fpga/Kconfig
wouldn't even be considered.
> +
> +config FPGA_MGR_SOCFPGA
> + tristate "Altera SOCFPGA FPGA Manager"
> + depends on ARCH_SOCFPGA
> + help
> + FPGA manager driver support for Altera SOCFPGA.
> +
> +endif # FPGA
> +
> endmenu
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 3313c52..ba6c5c5 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -6,3 +6,4 @@
> obj-$(CONFIG_FPGA) += fpga-mgr.o
>
> # FPGA Manager Drivers
> +obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> new file mode 100644
> index 0000000..706b80d
> --- /dev/null
> +++ b/drivers/fpga/socfpga.c
[..]
> +/*
> + * Step 9: write data to the FPGA data register
> + */
> +static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr,
> + const char *buf, size_t count)
> +{
> + struct socfpga_fpga_priv *priv = mgr->priv;
> + u32 *buffer_32 = (u32 *)buf;
Seems sketchy from an endianess perspective, but it may be okay if
SOCFPGA doesn't support BE (which my follow up question would be: why
not?). Same thing applies with seemingly cavalier usages of the
__raw_readl/writel variants.
Josh
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