linux-kernel - Re: [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask

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Message-ID: <alpine.DEB.2.11.1509221549420.5606@nanos>
Date:	Tue, 22 Sep 2015 15:50:30 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Boris Brezillon <boris.brezillon@...e-electrons.com>
cc:	Ludovic Desroches <ludovic.desroches@...el.com>,
	jason@...edaemon.net, marc.zyngier@....com,
	linux-kernel@...r.kernel.org, sasha.levin@...cle.com,
	linux-arm-kernel@...ts.infradead.org, nicolas.ferre@...el.com,
	alexandre.belloni@...e-electrons.com, Wenyou.Yang@...el.com
Subject: Re: [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask

On Tue, 22 Sep 2015, Boris Brezillon wrote:
> On Tue, 22 Sep 2015 12:27:08 +0200 (CEST)
> Thomas Gleixner <tglx@...utronix.de> wrote:
> > Why is this locking dgc->gc[0] and fiddling with some other generic
> > chip?
> 
> Actually, we always access the same set of registers for all irqs of the
> domain, and thus need to take the same lock (I chose the one contained
> in the first generic irqchip, but I guess it could work with the others
> too, as long as we always take the same one) before accessing them
> because the configuration is done in two steps:
> 
> 1/ specify the irq line you want to configure
> 2/ set the new configuration
> 
> Regarding register accesses, all generic chips are configured to
> point to the same registers, so accessing them from the 'base' generic
> chip or from the generic chip attached to the irq_data struct is the
> same, though I agree that using bgc would add some consistency to the
> implementation.

Fair enough. It just deserves a comment for the casual reader.

Thanks,

	tglx
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