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Date: Tue, 22 Sep 2015 11:12:15 -0700 From: Paul Burton <paul.burton@...tec.com> To: <linux-mips@...ux-mips.org> CC: Paul Burton <paul.burton@...tec.com>, <linux-kernel@...r.kernel.org>, James Hogan <james.hogan@...tec.com>, Markos Chandras <markos.chandras@...tec.com>, Ralf Baechle <ralf@...ux-mips.org> Subject: [PATCH 07/10] MIPS: CM: fix GCR_Cx_CONFIG PVPE mask The PVPE (or PVP in >= CM3) field is 10 bits wide, but the mask previously only covered the bottom 9 bits. Extend the mask to cover all 10 bits of the field. Signed-off-by: Paul Burton <paul.burton@...tec.com> --- arch/mips/include/asm/mips-cm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index d75b75e..2796424 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -324,7 +324,7 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) #define CM_GCR_Cx_CONFIG_PVPE_SHF 0 -#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0) +#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x3ff) << 0) /* GCR_Cx_OTHER register fields */ #define CM_GCR_Cx_OTHER_CORENUM_SHF 16 -- 2.5.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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