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Message-ID: <1442946260-26691-1-git-send-email-paul.burton@imgtec.com>
Date:	Tue, 22 Sep 2015 11:24:20 -0700
From:	Paul Burton <paul.burton@...tec.com>
To:	<linux-mips@...ux-mips.org>
CC:	Paul Burton <paul.burton@...tec.com>,
	Leonid Yegoshin <Leonid.Yegoshin@...tec.com>,
	<linux-kernel@...r.kernel.org>,
	James Hogan <james.hogan@...tec.com>,
	Markos Chandras <markos.chandras@...tec.com>,
	"Ralf Baechle" <ralf@...ux-mips.org>
Subject: [PATCH] MIPS: always use r4k_wait_irqoff for MIPSr6

Prior to release 6 of the MIPS architecture it has been implementation
dependent whether masked interrupts cause a wait instruction to return,
so the kernel has effectively had to maintain a whitelist of cores upon
which it is safe to use the r4k_wait_irqoff cpu_wait implementation.
With MIPSr6 this is no longer implementation dependent and
r4k_wait_irqoff can always be used.

Remove the existing I6400 case which will no longer ever be hit, and was
incorrect anyway since I6400 & r6 in general doesn't have the WII bit.

Signed-off-by: Paul Burton <paul.burton@...tec.com>
---

 arch/mips/kernel/idle.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index ab1478d..3e2b0b6 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -134,6 +134,16 @@ void __init check_wait(void)
 		return;
 	}
 
+	/*
+	 * MIPSr6 specifies that masked interrupts should unblock an executing
+	 * wait instruction, and thus that it is safe for us to use
+	 * r4k_wait_irqoff. Yippee!
+	 */
+	if (cpu_has_mips_r6) {
+		cpu_wait = r4k_wait_irqoff;
+		return;
+	}
+
 	switch (current_cpu_type()) {
 	case CPU_R3081:
 	case CPU_R3081E:
@@ -196,7 +206,6 @@ void __init check_wait(void)
 	case CPU_INTERAPTIV:
 	case CPU_M5150:
 	case CPU_QEMU_GENERIC:
-	case CPU_I6400:
 		cpu_wait = r4k_wait;
 		if (read_c0_config7() & MIPS_CONF7_WII)
 			cpu_wait = r4k_wait_irqoff;
-- 
2.5.3

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