linux-kernel - [PATCH 0/6] Support RIXI without fill bits

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Message-ID: <1442947373-13345-1-git-send-email-paul.burton@imgtec.com>
Date:	Tue, 22 Sep 2015 11:42:47 -0700
From:	Paul Burton <paul.burton@...tec.com>
To:	<linux-mips@...ux-mips.org>
CC:	Paul Burton <paul.burton@...tec.com>,
	"Steven J. Hill" <Steven.Hill@...tec.com>,
	Joshua Kinard <kumba@...too.org>,
	Leonid Yegoshin <Leonid.Yegoshin@...tec.com>,
	"Maciej W. Rozycki" <macro@...ux-mips.org>,
	Paul Gortmaker <paul.gortmaker@...driver.com>,
	<linux-kernel@...r.kernel.org>,
	James Hogan <james.hogan@...tec.com>,
	"Markos Chandras" <markos.chandras@...tec.com>,
	Ralf Baechle <ralf@...ux-mips.org>
Subject: [PATCH 0/6] Support RIXI without fill bits

This series fixes up the generated TLB exception handlers to take into
account cases where there are less fill bits in the Entry{Lo,Hi}
registers than there are software defined bits in a PTE. The most
notable case of this is when running a MIPS32 kernel on a MIPS64 system,
and given that RIXI is required on MIPSr6 support for it is required in
order to run MIPS32 kernels on MIPS64r6 CPUs.

Paul Burton (6):
  MIPS: tlbex: stop open-coding build_convert_pte_to_entrylo
  MIPS: tlbex: remove some RIXI redundancy
  MIPS: tlbex: share MIPS32 32 bit phys & MIPS64 64 bit phys code
  MIPS: tidy EntryLo bit definitions, add PFN
  MIPS: tlbex: avoid placing software PTE bits in Entry* PFN fields
  MIPS: allow RIXI for 32-bit kernels on MIPS64

 arch/mips/include/asm/cpu-features.h |  6 +--
 arch/mips/include/asm/mipsregs.h     | 12 ++---
 arch/mips/mm/tlbex.c                 | 89 ++++++++++++++++++++++--------------
 3 files changed, 59 insertions(+), 48 deletions(-)

-- 
2.5.3

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