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Message-ID: <1443109140-5406-5-git-send-email-yingjoe.chen@mediatek.com>
Date: Thu, 24 Sep 2015 23:38:59 +0800
From: Yingjoe Chen <yingjoe.chen@...iatek.com>
To: Russell King - ARM Linux <linux@....linux.org.uk>,
Matthias Brugger <matthias.bgg@...il.com>
CC: <devicetree@...r.kernel.org>, Arnd Bergmann <arnd@...db.de>,
Stephen Boyd <sboyd@...eaurora.org>,
<linux-kernel@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
<linux-mediatek@...ts.infradead.org>,
Sascha Hauer <kernel@...gutronix.de>,
Olof Johansson <olof@...om.net>, <srv_heupstream@...iatek.com>,
<linux-arm-kernel@...ts.infradead.org>,
Yingjoe Chen <yingjoe.chen@...iatek.com>
Subject: [PATCH v4 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
Add arch timer node to enable arch-timer support. MT8135 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This also set cpu enable-method to enable SMP.
Signed-off-by: Yingjoe Chen <yingjoe.chen@...iatek.com>
---
arch/arm/boot/dts/mt8135.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 08371db..c3c90f2 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -46,6 +46,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt81xx-tz-smp";
cpu0: cpu@0 {
device_type = "cpu";
@@ -72,6 +73,17 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ trustzone-bootinfo: trustzone-bootinfo@...02000 {
+ compatible = "mediatek,trustzone-bootinfo";
+ reg = <0 0x80002000 0 0x1000>;
+ };
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -97,6 +109,21 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <13000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
--
1.9.1
--
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