linux-kernel - Re: [PATCH V4 1/2] ACPI / EC: Fix broken 64bit big-endian users of 'global

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Message-ID: <3461169.v5xKdGLGjP@vostro.rjw.lan>
Date:	Sun, 27 Sep 2015 16:09:25 +0200
From:	"Rafael J. Wysocki" <rjw@...ysocki.net>
To:	James Bottomley <James.Bottomley@...senpartnership.com>
Cc:	Viresh Kumar <viresh.kumar@...aro.org>,
	Johannes Berg <johannes@...solutions.net>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Linaro Kernel Mailman List <linaro-kernel@...ts.linaro.org>,
	QCA ath9k Development <ath9k-devel@....qualcomm.com>,
	Intel Linux Wireless <ilw@...ux.intel.com>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Linux ACPI <linux-acpi@...r.kernel.org>,
	"open list:BLUETOOTH DRIVERS" <linux-bluetooth@...r.kernel.org>,
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	<alsa-devel@...a-project.org>
Subject: Re: [PATCH V4 1/2] ACPI / EC: Fix broken 64bit big-endian users of 'global_lock'

On Saturday, September 26, 2015 12:52:08 PM James Bottomley wrote:
> On Fri, 2015-09-25 at 22:58 +0200, Rafael J. Wysocki wrote:
> > On Friday, September 25, 2015 01:25:49 PM Viresh Kumar wrote:
> > > On 25 September 2015 at 13:33, Rafael J. Wysocki <rjw@...ysocki.net> wrote:
> > > > You're going to change that into bool in the next patch, right?
> > > 
> > > Yeah.
> > > 
> > > > So what if bool is a byte and the field is not word-aligned
> > > 
> > > Its between two 'unsigned long' variables today, and the struct isn't packed.
> > > So, it will be aligned, isn't it?
> > > 
> > > > and changing
> > > > that byte requires a read-modify-write.  How do we ensure that things remain
> > > > consistent in that case?
> > > 
> > > I didn't understood why a read-modify-write is special here? That's
> > > what will happen
> > > to most of the non-word-sized fields anyway?
> > > 
> > > Probably I didn't understood what you meant..
> > 
> > Say you have three adjacent fields in a structure, x, y, z, each one byte long.
> > Initially, all of them are equal to 0.
> > 
> > CPU A writes 1 to x and CPU B writes 2 to y at the same time.
> > 
> > What's the result?
> 
> I think every CPU's  cache architecure guarantees adjacent store
> integrity, even in the face of SMP, so it's x==1 and y==2.  If you're
> thinking of old alpha SMP system where the lowest store width is 32 bits
> and thus you have to do RMW to update a byte, this was usually fixed by
> padding (assuming the structure is not packed).  However, it was such a
> problem that even the later alpha chips had byte extensions.

OK, thanks!

Rafael

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