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Message-ID: <20150929114517.GA3534@pd.tnic>
Date: Tue, 29 Sep 2015 13:45:17 +0200
From: Borislav Petkov <bp@...en8.de>
To: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
Cc: mchehab@....samsung.com, dougthompson@...ssion.com,
linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 1/3] EDAC, amd64_edac: Extend scrub rate
programmability feature for F15hM60h
On Mon, Sep 28, 2015 at 06:43:12AM -0500, Aravind Gopalakrishnan wrote:
> For F15h M60h processor, the scrub rate control register has moved
> to F2 of PCI config space and is at a different offset from
> earlier processors. The minimun recommended scrub rate is also different.
> (Refer D18F2x1c9_dct[1:0][DramScrub] on Fam15hM60h BKDG)
>
> Modify the set_scrub_rate() and get_scrub_rate() functions so that
> they are aware of these changes.
>
> Tested on F15hM60h, Fam15h Models 00h-0fh and Fam10h systems and
> it works fine.
>
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
> ---
> drivers/edac/amd64_edac.c | 23 +++++++++++++++++++----
> drivers/edac/amd64_edac.h | 2 ++
> 2 files changed, 21 insertions(+), 4 deletions(-)
...
> @@ -216,12 +223,17 @@ static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
>
> if (pvt->fam == 0xf)
> min_scrubrate = 0x0;
> + else if (pvt->fam == 0x15 && pvt->model == 0x60)
> + min_scrubrate = 0x6;
>
> /* Erratum #505 */
> if (pvt->fam == 0x15 && pvt->model < 0x10)
> f15h_select_dct(pvt, 0);
>
> - return __set_scrub_rate(pvt->F3, bw, min_scrubrate);
> + if (pvt->fam == 0x15 && pvt->model == 0x60)
> + return __set_scrub_rate(pvt, bw, min_scrubrate);
> +
> + return __set_scrub_rate(pvt, bw, min_scrubrate);
This looks sloppy:
if (condition)
return function()
return function()
I ended up committing the version below. Other two applied too.
---
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
Date: Mon, 28 Sep 2015 06:43:12 -0500
Subject: [PATCH] EDAC, amd64_edac: Extend scrub rate support to F15hM60h
The scrub rate control register has moved to function 2 in PCI config
space and is at a different offset on family 0x15, models 0x60 and
later. The minimum recommended scrub rate has also changed. (Refer to
D18F2x1c9_dct[1:0][DramScrub] in Fam15hM60h BKDG).
Adjust set_scrub_rate() and get_scrub_rate() functions to accommodate
this.
Tested on F15hM60h, Fam15h, models 00h-0fh and Fam10h systems.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
Cc: linux-edac <linux-edac@...r.kernel.org>
Link: http://lkml.kernel.org/r/1443440593-2316-2-git-send-email-Aravind.Gopalakrishnan@amd.com
[ Cleanup conditionals. ]
Signed-off-by: Borislav Petkov <bp@...e.de>
---
drivers/edac/amd64_edac.c | 35 +++++++++++++++++++++++++----------
drivers/edac/amd64_edac.h | 2 ++
2 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 73aea40a9c89..ca03a736b106 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -173,7 +173,7 @@ static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
* scan the scrub rate mapping table for a close or matching bandwidth value to
* issue. If requested is too big, then use last maximum value found.
*/
-static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
+static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
{
u32 scrubval;
int i;
@@ -201,7 +201,14 @@ static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
scrubval = scrubrates[i].scrubval;
- pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F);
+ if (pvt->fam == 0x15 && pvt->model == 0x60) {
+ f15h_select_dct(pvt, 0);
+ pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
+ f15h_select_dct(pvt, 1);
+ pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
+ } else {
+ pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
+ }
if (scrubval)
return scrubrates[i].bandwidth;
@@ -217,11 +224,15 @@ static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
if (pvt->fam == 0xf)
min_scrubrate = 0x0;
- /* Erratum #505 */
- if (pvt->fam == 0x15 && pvt->model < 0x10)
- f15h_select_dct(pvt, 0);
+ if (pvt->fam == 0x15) {
+ /* Erratum #505 */
+ if (pvt->model < 0x10)
+ f15h_select_dct(pvt, 0);
- return __set_scrub_rate(pvt->F3, bw, min_scrubrate);
+ if (pvt->model == 0x60)
+ min_scrubrate = 0x6;
+ }
+ return __set_scrub_rate(pvt, bw, min_scrubrate);
}
static int get_scrub_rate(struct mem_ctl_info *mci)
@@ -230,11 +241,15 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
u32 scrubval = 0;
int i, retval = -EINVAL;
- /* Erratum #505 */
- if (pvt->fam == 0x15 && pvt->model < 0x10)
- f15h_select_dct(pvt, 0);
+ if (pvt->fam == 0x15) {
+ /* Erratum #505 */
+ if (pvt->model < 0x10)
+ f15h_select_dct(pvt, 0);
- amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
+ if (pvt->model == 0x60)
+ amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
+ } else
+ amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
scrubval = scrubval & 0x001F;
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 4bdec752d330..971dc12a0a1c 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -255,6 +255,8 @@
#define DCT_SEL_HI 0x114
+#define F15H_M60H_SCRCTRL 0x1C8
+
/*
* Function 3 - Misc Control
*/
--
2.3.5
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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