linux-kernel - Re: [PATCH] x86, perf: Handle multiple umask bits for BDW CYCLE

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Message-ID: <CABPqkBTg_53y5yqikcZtdVxXe6mXq_gnFyST0MCOhncqSn4awQ@mail.gmail.com>
Date:	Wed, 30 Sep 2015 14:21:44 -0700
From:	Stephane Eranian <eranian@...gle.com>
To:	LKML <linux-kernel@...r.kernel.org>
Cc:	"ak@...ux.intel.com" <ak@...ux.intel.com>,
	Peter Zijlstra <peterz@...radead.org>,
	"mingo@...e.hu" <mingo@...e.hu>, "Liang, Kan" <kan.liang@...el.com>
Subject: Re: [PATCH] x86, perf: Handle multiple umask bits for BDW CYCLE_ACTIVITY.*

Hi Andi,

> From: Andi Kleen <ak <at> linux.intel.com>
>
> The earlier constraint fix for Broadwell CYCLE_ACTIVITY.*
> forced umask 8 to counter 2. For this it used UEVENT,
> to match the complete umask.
>
> The event list for Broadwell has an additional
> CYC_ACT.STALLS_L1D_PENDIND event that uses umask 8, but also
> sets other bits in the umask.  The earlier strict umask match
> didn't handle this case.
>
I think this patch is not quite fixing the issue. Personnally I think, this is a
bit overkill. If you use L1D_PENDING (umask 8, cmask=8), then the UEVENT
version will handle this correctly. IF you have a different cmask,
then this is not
a valid combination for CYCLE_ACTIVITY. In any case, I think the change below
should give you want you wanted:

> Add a new UBIT_EVENT constraint macro that only matches
> the specified bits in the umask. Then use that macro
> to handle CYCLE_ACTIVITY.* on Broadwell.
>
> Reported-by: Grant Ayers
> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
> ---
>  arch/x86/kernel/cpu/perf_event.h       | 4 ++++
>  arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
> index 953a0e4..285fce3 100644
> --- a/arch/x86/kernel/cpu/perf_event.h
> +++ b/arch/x86/kernel/cpu/perf_event.h
> struct cpu_hw_events {
>  #define INTEL_UEVENT_CONSTRAINT(c, n)        \
>       EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
>
> +/* Constraint on specific umask bit only + event */
> +#define INTEL_UBIT_EVENT_CONSTRAINT(c, n)    \
> +     EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
> +
>  /* Like UEVENT_CONSTRAINT, but match flags too */
>  #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n)  \
>       EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 1d84b41..7ebc594 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> struct event_constraint intel_bdw_event_constraints[] = {
>       FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
>       FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
>       INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
> -     INTEL_UEVENT_CONSTRAINT(0x8a3, 0x4),    /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
> +     INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),        /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */

I think here you want to pass 0x80008a3, so that the cmask is used in
the comparison in x86_get_event_constraints().
--
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