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Message-ID: <878u7ojctb.fsf@ashishki-desk.ger.corp.intel.com>
Date: Wed, 30 Sep 2015 15:45:20 +0300
From: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
To: Mathieu Poirier <mathieu.poirier@...aro.org>,
gregkh@...uxfoundation.org, a.p.zijlstra@...llo.nl,
acme@...nel.org, mingo@...hat.com, corbet@....net
Cc: adrian.hunter@...el.com, zhang.chunyan@...aro.org,
mike.leach@....com, tor@...com, al.grant@....com,
pawel.moll@....com, linux-arm-kernel@...ts.infradead.org,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH 18/20] coresight: etm3x: pushing down perf configuration to tracer
Mathieu Poirier <mathieu.poirier@...aro.org> writes:
> +#define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN)
> +
> +static int etm_parse_event_config(struct etm_drvdata *drvdata,
> + struct perf_event *event)
> +{
> + u64 config = event->attr.config;
> +
> + /*
> + * At this time only cycle accurate and timestamp options are
> + * available. As such clear everything else that may have been
> + * configured and set the ETM control register based on what was
> + * requested.
> + */
> + config &= ETM3X_SUPPORTED_OPTIONS;
You want to make sure no bits outside of this mask are set in config,
though, and return -EINVAL. Below you're even checking for it:
> + if (etm_parse_event_config(drvdata, event))
> + return -EINVAL;
Regards,
--
Alex
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