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Message-ID: <04EAB7311EE43145B2D3536183D1A8445499CC87@GSjpTKYDCembx31.service.hitachi.net> Date: Thu, 1 Oct 2015 01:43:18 +0000 From: 河合英宏 / KAWAI,HIDEHIRO <hidehiro.kawai.ez@...achi.com> To: "'Peter Zijlstra'" <peterz@...radead.org> CC: Jonathan Corbet <corbet@....net>, Ingo Molnar <mingo@...nel.org>, "Eric W. Biederman" <ebiederm@...ssion.com>, "H. Peter Anvin" <hpa@...or.com>, Andrew Morton <akpm@...ux-foundation.org>, Thomas Gleixner <tglx@...utronix.de>, Vivek Goyal <vgoyal@...hat.com>, "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>, "x86@...nel.org" <x86@...nel.org>, "kexec@...ts.infradead.org" <kexec@...ts.infradead.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Michal Hocko <mhocko@...nel.org>, Ingo Molnar <mingo@...hat.com>, 平松雅巳 / HIRAMATU,MASAMI <masami.hiramatsu.pt@...achi.com> Subject: RE: [V4 PATCH 2/4] panic/x86: Allow cpus to save registers even if they are looping in NMI context > On Fri, Sep 25, 2015 at 08:28:07PM +0900, Hidehiro Kawai wrote: > > --- a/arch/x86/kernel/reboot.c > > +++ b/arch/x86/kernel/reboot.c > > @@ -718,6 +718,7 @@ void machine_crash_shutdown(struct pt_regs *regs) > > static nmi_shootdown_cb shootdown_callback; > > > > static atomic_t waiting_for_crash_ipi; > > +static int crash_ipi_done; > > > > static int crash_nmi_callback(unsigned int val, struct pt_regs *regs) > > { > > @@ -779,6 +780,7 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback) > > wmb(); > > > > smp_send_nmi_allbutself(); > > + crash_ipi_done = 1; /* Kick cpus looping in nmi context */ > > I would suggest using WRITE_ONCE() for that, because without the > volatile the compiler need not actually emit the store until after the > whole waiting thing _IF_ it can inline the whole thing. > > Currently udelay() will end up being a function call and will therefore > force the store to be emitted, but I'd rather not rely on that. OK, I use WRITE_ONCE(). Thanks! > > > > msecs = 1000; /* Wait at most a second for the other cpus to stop */ > > while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) { Hidehiro Kawai Hitachi, Ltd. Research & Development Group
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