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Message-ID: <20151002193238.GU12338@codeaurora.org>
Date: Fri, 2 Oct 2015 12:32:38 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Gabriel Fernandez <gabriel.fernandez@...aro.org>
Cc: Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@...il.com>,
Maxime Coquelin <maxime.coquelin@...com>,
Patrice Chotard <patrice.chotard@...com>,
Russell King <linux@....linux.org.uk>,
Michael Turquette <mturquette@...libre.com>,
Peter Griffin <peter.griffin@...aro.org>,
Pankaj Dev <pankaj.dev@...com>,
Olivier Bideau <olivier.bideau@...com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Fabian Frederick <fabf@...net.be>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
kernel@...inux.com, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 2/4] drivers: clk: st: PLL rate change implementation
for DVFS
On 08/24, Gabriel Fernandez wrote:
> Change A9 PLL rate, as per requirement from the cpufreq framework,
> for DVFS. For rate change, the A9 clock needs to be temporarily sourced
> from PLL external to A9 and then sourced back to A9-PLL
>
> Signed-off-by: Pankaj Dev <pankaj.dev@...com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...aro.org>
> ---
Applied to clk-next
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