linux-kernel - Re: Re: [PATCH v2] arm: Adding support for atomic half word exchange

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Message-id: <1912649938.590071444050653292.JavaMail.weblogic@epmlwas01c>
Date:	Mon, 05 Oct 2015 13:10:55 +0000 (GMT)
From:	Sarbojit Ganguly <ganguly.s@...sung.com>
To:	Will Deacon <will.deacon@....com>,
	Sarbojit Ganguly <ganguly.s@...sung.com>
Cc:	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"catalin.marinas@....com" <catalin.marinas@....com>,
	"Waiman.Long@...com" <Waiman.Long@...com>,
	"peterz@...radead.org" <peterz@...radead.org>,
	VIKRAM MUPPARTHI <vikram.m@...sung.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	SUNEEL KUMAR SURIMANI <suneel@...sung.com>,
	SHARAN ALLUR <sharan.allur@...sung.com>,
	"torvalds@...ux-foundation.org" <torvalds@...ux-foundation.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: Re: [PATCH v2] arm: Adding support for atomic half word exchange

Hello Will,

My sincere apologies for the format issue. This was due to the e-mail editor
which reformats the text.
I am reposting the patch, please let me know if it is ok this time.


v1-->v2 : Extended the guard code to cover the byte exchange case as 
well following opinion of Will Deacon.
Checkpatch has been run and issues were taken care of.

Since support for half-word atomic exchange was not there and Qspinlock
on ARM requires it, modified __xchg() to add support for that as well.
ARMv6 and lower does not support ldrex{b,h} so, added a guard code
to prevent build breaks.

Signed-off-by: Sarbojit Ganguly <ganguly.s@...sung.com>
---
 arch/arm/include/asm/cmpxchg.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 916a274..a53cbeb 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 
 	switch (size) {
 #if __LINUX_ARM_ARCH__ >= 6
+#if !defined(CONFIG_CPU_V6)
 	case 1:
 		asm volatile("@	__xchg1\n"
 		"1:	ldrexb	%0, [%3]\n"
@@ -49,6 +50,22 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 			: "r" (x), "r" (ptr)
 			: "memory", "cc");
 		break;
+
+		/*
+		 * Half-word atomic exchange, required
+		 * for Qspinlock support on ARM.
+		 */
+	case 2:
+		asm volatile("@	__xchg2\n"
+		"1:	ldrexh	%0, [%3]\n"
+		"	strexh	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#endif
 	case 4:
 		asm volatile("@	__xchg4\n"
 		"1:	ldrex	%0, [%3]\n"
-- 
1.9.1

------- Original Message -------
Sender : Will Deacon<will.deacon@....com>
Date : Oct 05, 2015 18:19 (GMT+05:30)
Title : Re: [PATCH v2] arm: Adding support for atomic half word exchange

On Mon, Oct 05, 2015 at 03:07:57AM +0000, Sarbojit Ganguly wrote:
> This is my second version of the patch which covers the byte exclusive
> case as pointed out by you.
> Please share your opinion on this.

The patch you posted is corrupted (the whitespace looks completely off)
so it can't be applied like this. Please take a look at your email/git
settings.

Will