linux-kernel - [PATCH v3 0/4] ST PLL improvement

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Message-Id: <1444032393-13433-1-git-send-email-gabriel.fernandez@linaro.org>
Date:	Mon,  5 Oct 2015 10:06:29 +0200
From:	Gabriel Fernandez <gabriel.fernandez@...aro.org>
To:	Maxime Coquelin <maxime.coquelin@...com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Gabriel Fernandez <gabriel.fernandez@...aro.org>
Cc:	Peter Griffin <peter.griffin@...aro.org>,
	Pankaj Dev <pankaj.dev@...com>,
	Olivier Bideau <olivier.bideau@...com>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Fabian Frederick <fabf@...net.be>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Srinivas Kandagatla <srinivas.kandagatla@...il.com>,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, kernel@...inux.com,
	linux-clk@...r.kernel.org
Subject: [PATCH v3 0/4] ST PLL improvement

Changes in v3:
 - reorganize patch 1 and 2 to avoid a break git bisect

Changes in v2:
 - Add const for st_pll4600c28_418_a9 structure
 - Use readl_relaxed_poll_timeout macro instead Jiffies
 - Add patch to enable stih418 A9 pll via DT.

This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3'

Gabriel Fernandez (4):
  drivers: clk: st: Support for enable/disable in Clockgen PLLs
  drivers: clk: st: PLL rate change implementation for DVFS
  drivers: clk: st: Correct the pll-type for A9 for stih418
  ARM: STi: DT: Add support for stih418 A9 pll

 .../devicetree/bindings/clock/st/st,clkgen-pll.txt |   1 +
 arch/arm/boot/dts/stih418-clock.dtsi               |   2 +-
 drivers/clk/st/clkgen-mux.c                        |   3 +
 drivers/clk/st/clkgen-pll.c                        | 468 ++++++++++++++++++++-
 drivers/clk/st/clkgen.h                            |   2 +
 5 files changed, 467 insertions(+), 9 deletions(-)

-- 
1.9.1

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