linux-kernel - [PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC

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Message-Id: <1444319786-36125-1-git-send-email-andriy.shevchenko@linux.intel.com>
Date:	Thu,  8 Oct 2015 18:56:26 +0300
From:	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:	linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, x86@...nel.org
Cc:	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Subject: [PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield

The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's
set the neccessary capability for that chip. See commit c54fdbb2823d (x86: Add
cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
---
 arch/x86/kernel/cpu/intel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 98a13db..209ac1e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 		switch (c->x86_model) {
 		case 0x27:	/* Penwell */
 		case 0x35:	/* Cloverview */
+		case 0x4a:	/* Merrifield */
 			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
 			break;
 		default:
-- 
2.5.3

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