lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20151009134619.GS32532@n2100.arm.linux.org.uk>
Date:	Fri, 9 Oct 2015 14:46:19 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Jisheng Zhang <jszhang@...vell.com>
Cc:	Marcin Wojtas <mw@...ihalf.com>,
	thomas.petazzoni@...e-electrons.com, andrew@...n.ch,
	ulf.hansson@...aro.org, jason@...edaemon.net, tawfik@...vell.com,
	jaz@...ihalf.com, linux-mmc@...r.kernel.org,
	linux-kernel@...r.kernel.org, nadavh@...vell.com,
	alior@...vell.com, gregory.clement@...e-electrons.com,
	linux-arm-kernel@...ts.infradead.org,
	sebastian.hesselbarth@...il.com
Subject: Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW
 card detect

On Fri, Oct 09, 2015 at 08:13:56PM +0800, Jisheng Zhang wrote:
> On Fri, 9 Oct 2015 03:03:52 +0200
> Marcin Wojtas <mw@...ihalf.com> wrote:
> 
> > Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
> > card detection. According to the SD sdandard this signal can be used for
> > this purpose combined with a pull-up resistor, implying inverted (active
> > low) polarization of a card detect. MMC standard does not support this
> > feature and does not operate with such connectivity of DAT3.
> > 
> > When using DAT3-based detection Armada 38x SDIO IP expects its internal
> > clock to be always on, which had to be ensured twofold:
> 
> What happen if runtime suspend disables its core clk and axi clk? I guess
> dat3-based detection isn't compatible with runtime pm. If so, do we also
> need to disable runtime pm in probe function?
> 
> > - Each time controller is reset by updating appropriate registers. On the
> >   occasion of adding new register @0x104, register @0x100 name is modified
> >   in order to the be aligned with Armada 38x documentation.
> > - Leaving the clock enabled despite power-down. For this purpose a new
> >   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.
> 
> As seen from other mails, Ulf calls for no more quirks...

Absolutely.

You have host->ops->set_clock, which you currently have set to
sdhci_set_clock().  If you need to do something different, please replace
that method with your own version - its fine to either wrap sdhci_set_clock()
or replace it entirely.

sdhci_set_clock() may benefit from being factored a little, so that it's
easier to replace parts of it.

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ