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Message-ID: <3E5A0FA7E9CA944F9D5414FEC6C712205DE5C9FD@ORSMSX106.amr.corp.intel.com>
Date:	Mon, 12 Oct 2015 18:55:04 +0000
From:	"Yu, Fenghua" <fenghua.yu@...el.com>
To:	Thomas Gleixner <tglx@...utronix.de>
CC:	H Peter Anvin <hpa@...or.com>, Ingo Molnar <mingo@...hat.com>,
	"Peter Zijlstra" <peterz@...radead.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	x86 <x86@...nel.org>,
	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	Marcelo Tosatti <mtosatti@...hat.com>
Subject: RE: [PATCH V2 0/5] x86: Intel Code Data Prioritization Support

> From: Thomas Gleixner [mailto:tglx@...utronix.de]
> Sent: Sunday, October 11, 2015 12:52 PM
> To: Yu, Fenghua
> Cc: H Peter Anvin; Ingo Molnar; Peter Zijlstra; linux-kernel; x86; Vikas
> Shivappa; Marcelo Tosatti
> Subject: Re: [PATCH V2 0/5] x86: Intel Code Data Prioritization Support
> 
> On Thu, 1 Oct 2015, Fenghua Yu wrote:
> 
> > This patch set supports Intel code data prioritization which is an
> > extension of cache allocation and allows to allocate code and data
> > cache seperately. It also includes cgroup interface for the user as
> > seperate patches. The cgroup interface for cache alloc is also resent.
> 
> Please sort out the interface discussion of the first set. When that is settled
> we can have a look at this part.

Yes, Peter Anvin is working on the interface with Tejun.

Thanks.

-Fenghua
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