linux-kernel - RE: [PATCH v10 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05

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Message-ID: <EE11001F9E5DDD47B7634E2F8A612F2E16242C92@lhreml503-mbs>
Date:	Tue, 13 Oct 2015 14:49:07 +0000
From:	Gabriele Paoloni <gabriele.paoloni@...wei.com>
To:	Arnd Bergmann <arnd@...db.de>, Bjorn Helgaas <helgaas@...nel.org>
CC:	"Wangzhou (B)" <wangzhou1@...ilicon.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	"jingoohan1@...il.com" <jingoohan1@...il.com>,
	"pratyush.anand@...il.com" <pratyush.anand@...il.com>,
	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"thomas.petazzoni@...e-electrons.com" 
	<thomas.petazzoni@...e-electrons.com>,
	"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
	"james.morse@....com" <james.morse@....com>,
	"Liviu.Dudau@....com" <Liviu.Dudau@....com>,
	"jason@...edaemon.net" <jason@...edaemon.net>,
	"robh@...nel.org" <robh@...nel.org>,
	"gabriel.fernandez@...aro.org" <gabriel.fernandez@...aro.org>,
	"Minghuan.Lian@...escale.com" <Minghuan.Lian@...escale.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	zhangjukuo <zhangjukuo@...wei.com>,
	qiuzhenfa <qiuzhenfa@...ilicon.com>,
	"liudongdong (C)" <liudongdong3@...wei.com>,
	qiujiang <qiujiang@...wei.com>,
	"xuwei (O)" <xuwei5@...ilicon.com>,
	"Liguozhu (Kenneth)" <liguozhu@...ilicon.com>,
	"Wangkefeng (Kevin)" <wangkefeng.wang@...wei.com>,
	Rob Herring <robh+dt@...nel.org>
Subject: RE: [PATCH v10 4/6] PCI: hisi: Add PCIe host support for HiSilicon
 SoC Hip05



> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@...db.de]
> Sent: Tuesday, October 13, 2015 12:12 PM
> To: Bjorn Helgaas
> Cc: Wangzhou (B); Bjorn Helgaas; jingoohan1@...il.com;
> pratyush.anand@...il.com; linux@....linux.org.uk;
> thomas.petazzoni@...e-electrons.com; Gabriele Paoloni;
> lorenzo.pieralisi@....com; james.morse@....com; Liviu.Dudau@....com;
> jason@...edaemon.net; robh@...nel.org; gabriel.fernandez@...aro.org;
> Minghuan.Lian@...escale.com; linux-pci@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org; zhangjukuo; qiuzhenfa; liudongdong (C);
> qiujiang; xuwei (O); Liguozhu (Kenneth); Wangkefeng (Kevin); Rob
> Herring
> Subject: Re: [PATCH v10 4/6] PCI: hisi: Add PCIe host support for
> HiSilicon SoC Hip05
> 
> On Monday 12 October 2015 16:35:45 Bjorn Helgaas wrote:
> >
> > > +{
> > > +     u64 addr;
> > > +     struct device_node *msi_node;
> > > +     struct resource res;
> > > +     struct device_node *np = pp->dev->of_node;
> > > +     struct hisi_pcie *pcie = to_hisi_pcie(pp);
> > > +
> > > +     msi_node = of_parse_phandle(np, "msi-parent", 0);
> > > +     if (!msi_node) {
> > > +             dev_err(pp->dev, "failed to find msi-parent\n");
> > > +             return -EINVAL;
> > > +     }
> > > +     of_address_to_resource(msi_node, 0, &res);
> >
> > Does this use the "msi-parent" node in the same way as other drivers
> > do?  I'm sure there must be other places where we extract struct
> > resource information from an "msi-parent" node, but I don't see them.
> >
> > I'm trying to verify that this isn't some kind of incompatible
> > extension of the "msi-parent" property.  I cc'd Arnd and Rob (DT
> > experts).
> 
> This is not ok, what this does is that it relies on a particular
> implementation of the MSI controller and directly accesses its
> registers.

Hi Arnd, thanks for reviewing.

What we do is to retrieve the msi-parent physical address and we store it
in our internal PCIe register locations...

So we do not operate directly on the msi controller registers...

So I wonder if the current implementation is Ok to retrieve the
msi-parent address....

Thanks

Gab


> 
> Instead, it should reference only the msi irq domain and let the
> driver for the MSI controller access the registers. Otherwise this
> code has to be rewritten once the same PCI host code appears in
> a machine that has a real GICv2m or GICv3.
> 
> 	Arnd
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