linux-kernel - RE: [PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes

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Message-ID: <FAF81613212CC5449F9A43554D3E454741A3936E@LEMAIL01.le.imgtec.org>
Date:	Wed, 14 Oct 2015 09:15:16 +0000
From:	Harvey Hunt <Harvey.Hunt@...tec.com>
To:	Ezequiel Garcia <ezequiel@...guardiasur.com.ar>
CC:	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	"Alex Smith" <Alex.Smith@...tec.com>,
	Zubair Kakakhel <Zubair.Kakakhel@...tec.com>,
	David Woodhouse <dwmw2@...radead.org>,
	Brian Norris <computersforpeace@...il.com>,
	Paul Burton <Paul.Burton@...tec.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mips@...ux-mips.org" <linux-mips@...ux-mips.org>,
	Alex Smith <alex@...x-smith.me.uk>
Subject: RE: [PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND
 device tree nodes

On 8 October 2015 at 22:23, Ezequiel Garcia < ezequiel@...guardiasur.com.ar> wrote:
>On 6 October 2015 at 13:27, Harvey Hunt <harvey.hunt@...tec.com> wrote:
>> From: Alex Smith <alex.smith@...tec.com>
>>
>> Add device tree nodes for the NEMC and BCH to the JZ4780 device tree,
>> and make use of them in the Ci20 device tree to add a node for the
>> board's NAND.
>>
>> Note that since the pinctrl driver is not yet upstream, this includes
>> neither pin configuration nor busy/write-protect GPIO pins for the
>> NAND. Use of the NAND relies on the boot loader to have left the pins
>> configured in a usable state, which should be the case when booted
>> from the NAND.
>>
>> Signed-off-by: Alex Smith <alex.smith@...tec.com>
>> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@...tec.com>
>> Cc: David Woodhouse <dwmw2@...radead.org>
>> Cc: Brian Norris <computersforpeace@...il.com>
>> Cc: Paul Burton <paul.burton@...tec.com>
>> Cc: linux-mtd@...ts.infradead.org
>> Cc: devicetree@...r.kernel.org
>> Cc: linux-kernel@...r.kernel.org
>> Cc: linux-mips@...ux-mips.org
>> Cc: Alex Smith <alex@...x-smith.me.uk>
>> Signed-off-by: Harvey Hunt <harvey.hunt@...tec.com>
>> ---
>> v6 -> v7:
>>  - Add nand-ecc-mode to DT.
>>  - Add nand-on-flash-bbt to DT.
>>
>> v4 -> v5:
>>  - New patch adding DT nodes for the NAND so that the driver can be
>>    tested.
>>
>>  arch/mips/boot/dts/ingenic/ci20.dts    | 54 ++++++++++++++++++++++++++++++++++
>>  arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 ++++++++++++++++
>>  2 files changed, 80 insertions(+)
>>
>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
>> index 9fcb9e7..453f1d3 100644
>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>> @@ -42,3 +42,57 @@
>>  &uart4 {
>>         status = "okay";
>>  };
>> +
>> +&nemc {
>> +       status = "okay";
>> +
>> +       nand: nand@1 {
>> +               compatible = "ingenic,jz4780-nand";
>> +               reg = <1 0 0x1000000>;
>> +
>
>Why is this in the ci20.dts instead of the SoC dtsi?
>
>Seems at least compatible and reg is not board-specific.
>
>Thanks,
>-- 
>Ezequiel García, VanguardiaSur
>www.vanguardiasur.com.ar

Hi Ezequiel,

The number of NAND nodes under the NEMC node is board specific - some devices
could have 2 NAND banks and others could have none. Including the compatible
property in jz4780.dtsi would imply that all JZ4780 boards have at least one NAND bank.

The size in the reg property would be the same for all NAND devices (as it refers to the
NAND registers), however the bank number would be different, so that can also be seen
as board specific.

Thanks,

Harvey