linux-kernel - Re: [PATCH v1 0/2] Common SerDes driver for TI's Keystone Platforms

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Message-ID: <CAL_JsqJTjCT8D-3OryFPEF8nnaPtrai7Mvf-gJRkh60aDixx-g@mail.gmail.com>
Date:	Thu, 15 Oct 2015 20:00:41 -0500
From:	Rob Herring <robh+dt@...nel.org>
To:	Russell King - ARM Linux <linux@....linux.org.uk>
Cc:	WingMan Kwok <w-kwok2@...com>, Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Kishon Vijay Abraham I <kishon@...com>,
	Roger Quadros <rogerq@...com>,
	Murali Karicheri <m-karicheri2@...com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Santosh Shilimkar <ssantosh@...nel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v1 0/2] Common SerDes driver for TI's Keystone Platforms

On Thu, Oct 15, 2015 at 11:51 AM, Russell King - ARM Linux
<linux@....linux.org.uk> wrote:
> On Thu, Oct 15, 2015 at 10:25:43AM -0400, WingMan Kwok wrote:
>> On TI's Keystone platforms, several peripherals such as the
>> gbe ethernet switch, 10gbe ethether switch and PCIe controller
>> require the use of a SerDes for converting SoC parallel data into
>> serialized data that can be output over a high-speed electrical
>> interface, and also converting high-speed serial input data
>> into parallel data that can be processed by the SoC.  The
>> SerDeses used by those peripherals, though they may be different,
>> are largely similar in functionality and setup.
>
> Given that serdes is not specific to TI, should this be specific to
> TI, or should there be an effort to come up with something which
> everyone who has serdes links can make use of?
>
> Serdes comes in multiple different forms: PCIe, 1G SGMII ethernet,
> 1000base-X ethernet, 10g ethernet, SATA... I'd hate to see a
> plethora of SoC specific stuff for this.

The licensed IP I've seen doesn't provide a standard register
interface, but just signals to the IP block. Same with PLL IP. So
we'll probably get to see vendors continue to differentiate on PHY
register design. :)

Rob
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