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Message-ID: <20151016151830.GZ3816@twins.programming.kicks-ass.net>
Date: Fri, 16 Oct 2015 17:18:30 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Will Deacon <will.deacon@....com>,
Paul McKenney <paulmck@...ux.vnet.ibm.com>
Cc: linux-kernel@...r.kernel.org, Oleg Nesterov <oleg@...hat.com>,
Ingo Molnar <mingo@...nel.org>
Subject: Q: schedule() and implied barriers on arm64
Hi,
IIRC Paul relies on schedule() implying a full memory barrier with
strong transitivity for RCU.
If not, ignore this email.
If so, however, I suspect AARGH64 is borken and would need (just like
PPC):
#define smp_mb__before_spinlock() smp_mb()
The problem is that schedule() (when a NO-OP) does:
smp_mb__before_spinlock();
LOCK rq->lock
clear_bit()
UNLOCK rq->lock
And nothing there implies a full barrier on AARGH64, since
smp_mb__before_spinlock() defaults to WMB, LOCK is an "ldaxr" or
load-acquire, UNLOCK is "stlrh" or store-release and clear_bit() isn't
anything.
Pretty much every other arch has LOCK implying a full barrier, either
because its strongly ordered or because it needs one for the ACQUIRE
semantics.
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