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Message-ID: <1445332391-30530-10-git-send-email-chaotian.jing@mediatek.com>
Date: Tue, 20 Oct 2015 17:13:11 +0800
From: Chaotian Jing <chaotian.jing@...iatek.com>
To: Ulf Hansson <ulf.hansson@...aro.org>
CC: Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
Seungwon Jeon <tgih.jun@...sung.com>,
Jaehoon Chung <jh80.chung@...sung.com>,
Kukjin Kim <kgene@...nel.org>,
Krzysztof Kozlowski <k.kozlowski@...sung.com>,
Barry Song <baohua@...nel.org>,
Hans de Goede <hdegoede@...hat.com>,
Chaotian Jing <chaotian.jing@...iatek.com>,
Lars-Peter Clausen <lars@...afoo.de>,
Javier Martinez Canillas <javier.martinez@...labora.co.uk>,
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Subject: [PATCH v2 9/9] arm64: dts: mediatek: add HS200/HS400/SDR50/SDR104 support
add HS200/HS400 support for eMMC
add SDR50/SDR104 support for SD
Signed-off-by: Chaotian Jing <chaotian.jing@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 4be66ca..a061221 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -70,10 +70,16 @@
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
- max-frequency = <50000000>;
+ max-frequency = <200000000>;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-hw-reset;
+ hs400-ds-delay = <0x14015>;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
non-removable;
};
@@ -83,9 +89,10 @@
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_uhs>;
bus-width = <4>;
- max-frequency = <50000000>;
+ max-frequency = <200000000>;
cap-sd-highspeed;
- sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
cd-gpios = <&pio 132 0>;
vmmc-supply = <&mt6397_vmch_reg>;
vqmmc-supply = <&mt6397_vmc_reg>;
@@ -154,13 +161,19 @@
<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_2mA>;
+ drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_2mA>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins_ds {
+ pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
@@ -178,13 +191,13 @@
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins_clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
--
1.8.1.1.dirty
--
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