linux-kernel - Re: [PATCHv4 23/24] arm64: Expose feature registers by emulating MRS

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Message-ID: <20151021085017.GF4801@e103592.cambridge.arm.com>
Date:	Wed, 21 Oct 2015 09:50:17 +0100
From:	Dave Martin <Dave.Martin@....com>
To:	"Suzuki K. Poulose" <suzuki.poulose@....com>
Cc:	linux-arm-kernel@...ts.infradead.org, mark.rutland@....com,
	Vladimir.Murzin@....com, steve.capper@...aro.org,
	ryan.arnold@...aro.org, ard.biesheuvel@...aro.org, aph@...hat.com,
	catalin.marinas@....com, will.deacon@....com,
	linux-kernel@...r.kernel.org, edward.nevill@...aro.org,
	james.morse@....com, andre.przywara@....com, marc.zyngier@....com,
	christoffer.dall@...aro.org
Subject: Re: [PATCHv4 23/24] arm64: Expose feature registers by emulating MRS

On Mon, Oct 19, 2015 at 02:25:00PM +0100, Suzuki K. Poulose wrote:
> This patch adds the hook for emulating MRS instruction to
> export the 'user visible' value of supported system registers.
> We emulate only the following id space for system registers:
> 	Op0=0, Op1=0, CRn=0.

[...]

> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 896a821..c44da31 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c

[...]

> @@ -908,3 +910,106 @@ void __init setup_cpu_features(void)
>  		pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
>  			L1_CACHE_BYTES, cls);
>  }
> +
> +/*
> + * We emulate only the following system register space.
> + * 	Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0 - 7]

nit: ^ whitespace, no need to fix unless respinning the series

[...]

> +/*
> + * With CRm = 0, id should be one of :
> + *	MIDR_EL1
> + *	MPIDR_EL1
> + *  	REVIDR_EL1

nit: ^ whitespace

[...]

Cheers
---Dave

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