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Message-Id: <1445422125-72075-1-git-send-email-mika.westerberg@linux.intel.com>
Date:	Wed, 21 Oct 2015 13:08:42 +0300
From:	Mika Westerberg <mika.westerberg@...ux.intel.com>
To:	Linus Walleij <linus.walleij@...aro.org>
Cc:	Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org
Subject: [PATCH 0/3] pinctrl: Add support for Intel Broxton SoC

Hi,

This series adds pinctrl/GPIO support for Intel Broxton SoC. The GPIO
hardware is based on the same design already found in Intel Skylake
(Sunrisepoint PCH).

This series adds a new driver pinctrl-broxton.c which reuses the existing
Intel pinctrl core functionality and provides Broxton specific pin
configuration.

Mika Westerberg (3):
  pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt
  pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs
  pinctrl: intel: Add Intel Broxton pin controller support

 drivers/pinctrl/intel/Kconfig           |    8 +
 drivers/pinctrl/intel/Makefile          |    1 +
 drivers/pinctrl/intel/pinctrl-broxton.c | 1065 +++++++++++++++++++++++++++++++
 drivers/pinctrl/intel/pinctrl-intel.c   |   68 +-
 4 files changed, 1123 insertions(+), 19 deletions(-)
 create mode 100644 drivers/pinctrl/intel/pinctrl-broxton.c

-- 
2.6.1

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