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Message-ID: <20151021114025.GE3270@x1>
Date: Wed, 21 Oct 2015 12:40:25 +0100
From: Lee Jones <lee.jones@...aro.org>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Mika Westerberg <mika.westerberg@...el.com>,
linux-kernel@...r.kernel.org,
Mika Westerberg <mika.westerberg@...ux.intel.com>
Subject: Re: [PATCH v1 2/2] mfd: lpss: Add Intel Broxton PCI IDs
On Wed, 21 Oct 2015, Andy Shevchenko wrote:
> Intel Broxton has the same LPSS block than Intel Sunrisepoint so add
> Broxton PCI IDs to the list.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> ---
> drivers/mfd/intel-lpss-pci.c | 45 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
Applied, thanks.
> diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
> index 9236dff..5bfdfcc 100644
> --- a/drivers/mfd/intel-lpss-pci.c
> +++ b/drivers/mfd/intel-lpss-pci.c
> @@ -70,7 +70,52 @@ static const struct intel_lpss_platform_info spt_uart_info = {
> .clk_con_id = "baudclk",
> };
>
> +static const struct intel_lpss_platform_info bxt_info = {
> + .clk_rate = 100000000,
> +};
> +
> +static const struct intel_lpss_platform_info bxt_uart_info = {
> + .clk_rate = 100000000,
> + .clk_con_id = "baudclk",
> +};
> +
> +static const struct intel_lpss_platform_info bxt_i2c_info = {
> + .clk_rate = 133000000,
> +};
> +
> static const struct pci_device_id intel_lpss_pci_ids[] = {
> + /* BXT */
> + { PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0aae), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0ab0), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0ab2), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0ab4), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0ab6), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0ab8), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0aba), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x0abc), (kernel_ulong_t)&bxt_uart_info },
> + { PCI_VDEVICE(INTEL, 0x0abe), (kernel_ulong_t)&bxt_uart_info },
> + { PCI_VDEVICE(INTEL, 0x0ac0), (kernel_ulong_t)&bxt_uart_info },
> + { PCI_VDEVICE(INTEL, 0x0ac2), (kernel_ulong_t)&bxt_info },
> + { PCI_VDEVICE(INTEL, 0x0ac4), (kernel_ulong_t)&bxt_info },
> + { PCI_VDEVICE(INTEL, 0x0ac6), (kernel_ulong_t)&bxt_info },
> + { PCI_VDEVICE(INTEL, 0x0aee), (kernel_ulong_t)&bxt_uart_info },
> + /* APL */
> + { PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5ab0), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5ab2), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5ab4), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5ab6), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5ab8), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5aba), (kernel_ulong_t)&bxt_i2c_info },
> + { PCI_VDEVICE(INTEL, 0x5abc), (kernel_ulong_t)&bxt_uart_info },
> + { PCI_VDEVICE(INTEL, 0x5abe), (kernel_ulong_t)&bxt_uart_info },
> + { PCI_VDEVICE(INTEL, 0x5ac0), (kernel_ulong_t)&bxt_uart_info },
> + { PCI_VDEVICE(INTEL, 0x5ac2), (kernel_ulong_t)&bxt_info },
> + { PCI_VDEVICE(INTEL, 0x5ac4), (kernel_ulong_t)&bxt_info },
> + { PCI_VDEVICE(INTEL, 0x5ac6), (kernel_ulong_t)&bxt_info },
> + { PCI_VDEVICE(INTEL, 0x5aee), (kernel_ulong_t)&bxt_uart_info },
> /* SPT-LP */
> { PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info },
> { PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info },
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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