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Message-ID: <20151022102959.09f0a1f4@OPI2>
Date:	Thu, 22 Oct 2015 10:29:59 +0200
From:	Jean-Francois Moine <moinejf@...e.fr>
To:	Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc:	Jens Kuske <jenskuske@...il.com>, devicetree@...r.kernel.org,
	Vishnu Patekar <vishnupatekar0510@...il.com>,
	Emilio López <emilio@...pez.com.ar>,
	Michael Turquette <mturquette@...libre.com>,
	linux-sunxi@...glegroups.com, linux-kernel@...r.kernel.org,
	Hans de Goede <hdegoede@...hat.com>,
	Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh+dt@...nel.org>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Linus Walleij <linus.walleij@...aro.org>,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On Thu, 22 Oct 2015 10:05:08 +0200
Maxime Ripard <maxime.ripard@...e-electrons.com> wrote:

> > +		uart0: serial@...28000 {
> > +			compatible = "snps,dw-apb-uart";
> > +			reg = <0x01c28000 0x400>;
> > +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			clocks = <&bus_gates 112>;
> > +			resets = <&bus_rst 208>;  
> 
> It's a bit weird that the clocks and reset indices don't match,
> usually they do.
> 
> What's even weirder is that there's a 96 offset between the two (4 *
> 32), is this expected?

Yes, this is conform to the H3 documentation.

-- 
Ken ar c'hentañ	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/
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