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Message-ID: <5628C8E2.6040703@gmail.com>
Date: Thu, 22 Oct 2015 13:30:42 +0200
From: Jens Kuske <jenskuske@...il.com>
To: Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc: Jean-Francois Moine <moinejf@...e.fr>, devicetree@...r.kernel.org,
Vishnu Patekar <vishnupatekar0510@...il.com>,
Emilio López <emilio@...pez.com.ar>,
Michael Turquette <mturquette@...libre.com>,
linux-sunxi@...glegroups.com, linux-kernel@...r.kernel.org,
Hans de Goede <hdegoede@...hat.com>,
Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Linus Walleij <linus.walleij@...aro.org>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI
On 22/10/15 11:14, Maxime Ripard wrote:
> On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote:
>> On Thu, 22 Oct 2015 10:47:35 +0200
>> Maxime Ripard <maxime.ripard@...e-electrons.com> wrote:
>>
>>> Not really. The uart0 reset is the bit 16, in the reset register 4.
>>>
>>> 4 * 32 + 16 = 44.
>>>
>>> Not 112, but still not 208 either.
>>
>> The registers are numbered 1..5, then
>>
>> (4 - 1) * 32 + 16 = 112
>
> Not on my version, and even then, UARTs are on the last reset
> register, which would still make 144.
>
> Maxime
>
There are holes between reg2 and reg3 and reg4 for some reason, but even
if we would correct that with some of_xlate() function they won't
completely line up with the gates.
Jens
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