linux-kernel - [PATCH v2 2/4] KVM: X86: LBR MSRs of supported CPU types

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Message-ID: <1445591718-5720-3-git-send-email-jianjay.zhou@huawei.com>
Date:	Fri, 23 Oct 2015 17:15:16 +0800
From:	Jian Zhou <jianjay.zhou@...wei.com>
To:	<kvm@...r.kernel.org>, <pbonzini@...hat.com>, <gleb@...nel.org>,
	<tglx@...utronix.de>, <mingo@...hat.com>, <hpa@...or.com>,
	<x86@...nel.org>, <linux-kernel@...r.kernel.org>
CC:	<herongguang.he@...wei.com>, <zhang.zhanghailiang@...wei.com>,
	<weidong.huang@...wei.com>, <peter.huangpeng@...wei.com>,
	Jian Zhou <jianjay.zhou@...wei.com>
Subject: [PATCH v2 2/4] KVM: X86: LBR MSRs of supported CPU types

Macros about LBR MSRs.

Signed-off-by: Jian Zhou <jianjay.zhou@...wei.com>
Signed-off-by: Stephen He <herongguang.he@...wei.com>
---
 arch/x86/include/asm/msr-index.h | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b98b471..2afcacd 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -68,10 +68,32 @@

 #define MSR_LBR_SELECT			0x000001c8
 #define MSR_LBR_TOS			0x000001c9
+#define MSR_LBR_CORE_FROM		0x00000040
+#define MSR_LBR_CORE_TO 		0x00000060
+#define MAX_NUM_LBR_MSRS		128
+/* Pentium4/Xeon(based on NetBurst) LBR */
+#define MSR_PENTIUM4_LER_FROM_LIP	0x000001d7
+#define MSR_PENTIUM4_LER_TO_LIP		0x000001d8
+#define MSR_PENTIUM4_LBR_TOS		0x000001da
+#define MSR_LBR_PENTIUM4_FROM		0x00000680
+#define MSR_LBR_PENTIUM4_TO		0x000006c0
+#define SIZE_PENTIUM4_LBR_STACK 	16
+/* Core2 LBR */
+#define MSR_LBR_CORE2_FROM		MSR_LBR_CORE_FROM
+#define MSR_LBR_CORE2_TO		MSR_LBR_CORE_TO
+#define SIZE_CORE2_LBR_STACK		4
+/* Atom LBR */
+#define MSR_LBR_ATOM_FROM		MSR_LBR_CORE_FROM
+#define MSR_LBR_ATOM_TO 		MSR_LBR_CORE_TO
+#define SIZE_ATOM_LBR_STACK		8
+/* Nehalem LBR */
 #define MSR_LBR_NHM_FROM		0x00000680
 #define MSR_LBR_NHM_TO			0x000006c0
-#define MSR_LBR_CORE_FROM		0x00000040
-#define MSR_LBR_CORE_TO			0x00000060
+#define SIZE_NHM_LBR_STACK		16
+/* Skylake LBR */
+#define MSR_LBR_SKYLAKE_FROM		MSR_LBR_NHM_FROM
+#define MSR_LBR_SKYLAKE_TO		MSR_LBR_NHM_TO
+#define SIZE_SKYLAKE_LBR_STACK		32

 #define MSR_LBR_INFO_0			0x00000dc0 /* ... 0xddf for _31 */
 #define LBR_INFO_MISPRED		BIT_ULL(63)
--
1.7.12.4


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